tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:forum-32034Nabble - Architecture2024-03-29T03:01:26Ztag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037677the slide of lecture 5 lost.2024-03-26T07:01:11Z2024-03-26T07:01:11Zjqma
Help needed, the slides for Lecture 5 on the nand2teris website cannot be viewed. When I click the link, it shows a 404 error. I would be extremely grateful if someone could provide me with this material.
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036406Figure 4.7 Array processing example, using pointer-based access to array elements.2021-10-12T06:26:12Z2021-10-12T06:26:12Zouverson
4.3 Hack Programming >
<br/>Example 3 >
<br/>Figure 4.7 Array processing example, using pointer-based access to array elements.
<br/><br/>Pseudocode:
<br/>-----------
<br/>// Program: PointerDemo
<br/>// Starting at base adress R0,
<br/>// sets the first R1 words to -1
<br/> n = 0
<br/>LOOP:
<br/> if (n == R1) goto END
<br/> *(R0 + n) = -1
<br/> n = n + 1
<br/> goto LOOP
<br/>END:
<br/>-----------
<br/><br/>The issue I had with this pseudocode:
<br/><br/>If I place value 10 in R1 and then run the program:
<br/><br/>Iteration #1 sets R0 to -1
<br/>Iteration #2 sets R1 to -1
<br/>R1 is now -1 and not 10; the program runs until memory is gone (I assume.)
<p>Posted in <a href="/Chapter-4-f32603.html">Chapter 4</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037496I'm unsure why this isn't loading in to the hardware simulator2023-11-28T14:45:42Z2023-11-28T14:45:42ZKtesibios
I know that the program won't load into the hardware sim, if the program is wrong, however i can't see where I'm going wrong. This is the code that I have made for the CPU. I can't seem to find where I have gone wrong
<br/><br/><br/>CHIP CPU {
<br/><br/> IN inM[16], // M value input (M = contents of RAM[A])
<br/> instruction[16], // Instruction for execution
<br/> reset; // Signals whether to re-start the current
<br/> // program (reset==1) or continue executing
<br/> // the current program (reset==0).
<br/><br/> OUT outM[16], // M value output
<br/> writeM, // Write to M?
<br/> addressM[15], // Address in data memory (of M)
<br/> pc[15]; // address of next instruction
<br/><br/> PARTS:
<br/> // Put your code here:
<br/> Mux16(a=aregout, b=inM, sel=instruction[12], out=aluy);
<br/> ALU(x=alux, y=aluy, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=outM, out=aluout, zr=zr, ng=ng);
<br/> DRegister(in=aluout, load=instruction[4], out=alux);
<br/> ARegister(in=ain, load=instruction[5], out=aregout, out=addressM);
<br/> Mux16(a=instruction, b=aluout, sel=instruction[15], out=ain);
<br/> And(a=instruction[2], b=ng, out=jlt);
<br/> And(a=instruction[1], b=zr, out=jeq);
<br/> Nand(a=zr, b=ng, out=gt);
<br/> And(a=gt, b=instruction[0], out=jgt);
<br/> Or(a=jgt, b=jlt, out=jm);
<br/> Or(a=jr, b=jeq, out=pcl);
<br/> PC(in=aregout, load=pcl, inc=true, reset=reset, out=pc);
<br/> And(a=instruction[3], b=instruction[3], out=writeM);
<br/>}
<br/>
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037487stuck with fill.asm2023-11-19T03:27:00Z2023-11-19T03:27:00Zfmiren
Below is my attempt for doing fill.asm. I wrote comments to explain what I'm trying to do in each block. Could you please have a look at it? Any hint / help is appreciated.
<br/>In a nutshell, I check whether KBD (R24576) is 0 or 1. Then depending on it, I go to the corresponding line where I run nested loop for rows and columns, and make the screen black or white accordingly. At least this is what I believe my code does.
<br/>Other than any specific error, is it even the proper way to arrange logic for this assignment? Is it possible to do it without nested loop? I'd like to get suggestions how I can improve it and fix my bugs.
<br/><br/>@LOOP
<br/> @R24576
<br/> D=M // D=M[24576]
<br/> @29
<br/> D;JEQ // if D == 0, goto 29th line
<br/> @6
<br/> 0;JNE // if D != 0, goto 6th line
<br/><br/> // Blacken the screen
<br/> @16384
<br/> D=A
<br/> @i
<br/> M=D // i=16384
<br/><br/> // goto the END if i == 24576
<br/> @i
<br/> D=M // D=i
<br/> @24576
<br/> D=D-A // D=D-24576
<br/> @END
<br/> D;JGT // goto END if D > 0; this line ensures that outer loop will run from 16384 to 24576.
<br/>
<br/> // goto the the outer loop if j == 16
<br/> @j
<br/> M=0 // j=0
<br/> @j
<br/> D=M // D=j
<br/> @16
<br/> D=D-A // D=D-16
<br/> @28
<br/> D;JGT // the end of inner loop - go to 28th line, i.e., i=i+1.
<br/><br/> @SCREEN
<br/> M=1 // M=1, i.e., screen blackens.
<br/> @j
<br/> M=M+1 // j=j+1, inner loop
<br/> @i
<br/> M=M+1 // i=i+1, outer loop
<br/>
<br/>
<br/> // Whiten the screen
<br/> @16384
<br/> D=A
<br/> @i
<br/> M=D // i=16384
<br/><br/> // goto the END if i == 24576
<br/> @i
<br/> D=M // D=i
<br/> @24576
<br/> D=D-A // D=D-24576
<br/> @END
<br/> D;JGT // goto END if D > 0; this line ensures that outer loop will run from 16384 to 24576.
<br/>
<br/> // goto the the outer loop if j == 16
<br/> @j
<br/> M=0 // j=0
<br/> @j
<br/> D=M // D=j
<br/> @16
<br/> D=D-A // D=D-16
<br/> @56
<br/> D;JGT // the end of inner loop - go to 56th line, i.e., i=i+1.
<br/><br/> @SCREEN
<br/> M=0 // M=0, i.e., screen returns to white.
<br/> @j
<br/> M=M+1 // j=j+1, inner loop
<br/> @i
<br/> M=M+1 // i=i+1, outer loop
<br/><br/>
<br/>(END)
<br/> @END
<br/> 0;JMP // infinite loop
<br/><br/><br/>
<p>Posted in <a href="/Chapter-4-f32603.html">Chapter 4</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037477General: Understanding of CPU/Memory communication2023-11-10T01:29:54Z2023-11-10T01:29:54Zdsguy
Hi, I recently finished part 1 of the course and I must say I've been loving it, learned a ton and really looking forward to continuing the journey with part 2.
<br/><br/>However, there is still one thing that I cannot wrap my head around. I've been doing quite some research and whenever I thought I understood the concept, then another source popped up with explanations seemingly contradicting what I had thought I understood before.
<br/>I am pretty sure I am just not really understanding a core piece of <b>terminology</b> or whatever, so hopefully someone here can clear things up for me.
<br/><br/>High level, I am confused about how the CPU and Memory exchange pieces of information of varying width, how the former operates on them and how the latter stores them:
<br/><br/>* Computers usually come in architectures of X-bit (usually 32 or 64); at the beginning of this course, when building out all the chips, I was under the impression that a X-bit computer <b>must</b> be build from X-bit parts - is this assumption correct or does it only refer to bus width? E.g. can I have 2X-bit registers in X-bit computer?
<br/><br/>* I am using a 64-bit laptop, yet when I hexdump e.g. a file that contains the string "hello", I can see that each letter is stored in one byte - <b>each with its own memory address</b>. This is what I don't understand! Does that mean at some place between the ALU and the Memory there is a "thing" that fans out a single 64-bit instruction into (in this case) 5 instructions? How would that work?
<br/><br/>* Memory chips - if I understood correctly - can be much wider than regular computer architectures, like 128, 256 bit wide. If I have a chip with a 256 bit register, is every register simply partitioned into 32 byte parts, each with their own address (through <i>some means</i>)?
<br/><br/>* How does a 64-bit CPU operate on multiple bytes retrieved from Memory? Say, the "hello" string stored in Memory is retrieved and displayed on a screen, is this done in a single operation, can the magical "thing" I don't understand take 5 smaller instructions and glue them together to one 64-bit instruction or is it maybe simply done in multiple clock cycles (which seems unlikely for me since it sounds like quite a waste).
<br/><br/>* If my assumptions from above are correct, where does Hack fit in here? Within Hack, everything is 16-bit and going back and forth is very logical to me. Is this for simplicity reasons?
<br/><br/>At some point during my research I understood that storing information such as a single character in 16, 32 or 64-bit memory locations is of course a total waste of space and storing individual bytes makes much more sense. I just feel like I don't really understand how varying widths of information and physical chips can easily communicate with each other.
<br/><br/>Thanks (and sorry for the long post :D)
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037411project 5- CPU2023-10-04T10:50:36Z2023-10-04T10:50:36Zmeir
hi,
<br/>I don't understand why the simulator can't even load my program,
<br/>help me please..
<br/><br/>CHIP CPU {
<br/><br/> IN inM[16], // M value input (M = contents of RAM[A])
<br/> instruction[16], // Instruction for execution
<br/> reset; // Signals whether to re-start the current
<br/> // program (reset==1) or continue executing
<br/> // the current program (reset==0).
<br/><br/> OUT outM[16], // M value output
<br/> writeM, // Write to M?
<br/> addressM[15], // Address in data memory (of M)
<br/> pc[15]; // address of next instruction
<br/><br/> PARTS:
<br/> // Put your code here:
<br/> Mux16(a=instruction, b=outalu ,sel=instruction[15] ,out=aorc);
<br/> Not(in=instruction[15] ,out=typea);
<br/> Or(a=typea ,b=instruction[5] ,out=loada);
<br/> ARegister(in=aorc ,load=loada ,out=addressM, out=outa);
<br/> DRegister(in=outalu ,load=instruction[4] ,out=outd);
<br/> Mux16(a=outa ,b=inM ,sel=instruction[11] ,out=aorm);
<br/> ALU(x=outd ,y=aorm ,zx=instruction[11] ,nx=instruction[10] ,zy=instruction[9] ,ny=instruction[8] ,f=instruction[7] ,no=instruction[6] ,out=outalu, out=outM ,zr=eq ,ng=ld);
<br/> And(a=instruction[15] ,b=instruction[3] ,out=writeM);
<br/>
<br/> PC(in=outa ,load=g ,inc=True ,reset=reset ,out= pc);
<br/>
<br/> Or(a=ld ,b=eq ,out=or0);
<br/> Not(in=or0 ,out=or1);
<br/> Or(a=instruction[1] ,b=instruction[2] ,out=m1);
<br/> Not(in=m1 ,out=m2);
<br/> And(a=or1 ,b=m2 ,out=m3);
<br/> And(a=m3 ,b=instruction[0] ,out=m!);
<br/>
<br/><br/> And(a=instruction[1] ,b=eq ,out=e1);
<br/> Or(a=instruction[0] ,b=instruction[2] ,out=e2);
<br/> Not(in=e2 ,out=e3);
<br/> And(a=e3 ,b=e1 ,out=e!);
<br/>
<br/> Or(a=e! ,b=m!,out=i!);
<br/>
<br/> Or(a=instruction[0] ,b=instruction[1] ,out=r1);
<br/> Not(in=r1 ,out=r2);
<br/> And(a=ld ,b=instruction[2] ,out=r3 );
<br/> And(a=r3 ,b=r2 ,out=r!);
<br/>
<br/> And(a=instruction[0] ,b=instruction[2] ,out=s1 );
<br/> Or(a=instruction[1] ,b=eq ,out=s2);
<br/> Not(in=s2 ,out=s3);
<br/> And(a=s3 ,b=s1 ,out=s!);
<br/>
<br/> Or(a=r! ,b=e!,out=o!);
<br/>
<br/> And(a=instruction[0] ,b=instruction[1] ,out=n1);
<br/> And(a=n1 ,b=instruction[2], out=n!);
<br/>
<br/> Or(a=m! ,b=e! ,out=more );
<br/> Or(a=i! ,b=r! ,out=iorr );
<br/> Or(a=s! ,b=o! ,out=soro );
<br/> Or(a=n! ,b=more ,out=normore);
<br/> Or(a=iorr ,b=soro ,out=iorrorsoro);
<br/> Or(a=normore ,b=iorrorsoro ,out=orsum);
<br/> And(a=orsum ,b=instruction[15] ,out=g);
<br/>}
<p>Posted in <a href="/Project-5-f32606.html">Project 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4032304Stuck on CPU implementation2018-08-11T09:24:10Z2018-08-11T09:24:10Zburge91
Not sure what to do. Not asking for tips, just moaning. Half the battle is confidence really, since I'm not even trying, it's like I've decided "this is where I will fail" for whatever reason I have decided that.
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037310Screen memory mapping2023-08-09T01:21:52Z2023-08-09T01:21:52ZShiv
Isn't 8000 all memory address for screen or more than 8000?
<br/><br/>I work on Fill.asm project and when i type a key, the whole screen seems to be turned black. But when i test with FillAutomatic.tst, it fails. I'm guessing 8000 might not be enough to fill the whole screen.
<br/><br/>Could anybody help me? Thank you for looking this.
<p>Posted in <a href="/Chapter-4-f32603.html">Chapter 4</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037283Project 5 - External tests2023-07-10T12:38:51Z2023-07-10T12:38:51ZWBahn
The test files for the CPU and the three computer programs (Add, Max, and Rect) have two versions, one of which is appended with "-external". Several people have wondered about these test files, as they are not explicitly mentioned in the text (1st Edition, anyway).
<br/><br/>The text recommends that students use the built-in components for the Chapter 5 projects. Namely, the RAM16K, the ARegister, the DRegister, and the PC. The reason, as mentioned in the text, is that these built-in parts include GUI elements that are useful for debugging. But using the internal parts also makes some additional variables visible to the test scripts, such as the contents of the A and D registers, that are not accessible if the normal Register part is used to implement them within the CPU.
<br/><br/>So, the normal version of the test scripts assume that the HDL code uses the internal parts. But if you want to run your program using your parts, you can do that. However, the test files have to be modified so that they don't attempt to access variables that are no longer available. That is what the "-external" versions of the test scripts do.
<br/><br/>To be clear, there is no requirement that you use the external tests. They are merely provided to give you the option of seeing how your computer runs with more of your components.
<br/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037272Project 4 - Mult.asm: Things to consider2023-07-08T23:08:54Z2023-07-08T23:08:54ZWBahn
Remember what is important in this project -- writing a program that produces the specified result. Do not worry about getting the result in the most elegant or efficient way -- that's not the goal, the goal is to get an introduction to writing and running an assembly language program for the Hack platform. So don't make the problem harder than it is -- the constraints that the contents in R0 and R1 will not be negative and that their product will be less than 32768, means that even a very brute force approach will run in a reasonable amount of time.
<br/><br/>The rest of this post is completely optional -- do not let yourself get sidetracked (unless you want to).
<br/><br/>Once you do have a working program, you might choose to see if you can improve it. Not only will this get you more experience with the Hack assembly language and how to bend it to your will, it might help you when you later need to implement the multiplication function for the Math operating system library.
<br/><br/>Consider the following: When solving problems in most engineering disciplines (and many non-engineering disciplines), a good approach is to first get ANY solution that correctly solves the problem, even if you know up front that there are things about it that will render it unacceptable as the ultimate solution. That initial correct solution is often a good starting point for figuring out how to improve the solution, perhaps incrementally, until you are left with an acceptable solution that may or may not bear much resemblance to that first one. Even if you end up scrapping the original solution and starting down a different path from scratch, what you learned about how to solve the problem and why the original solution was a dead-end will usually pay valuable dividends as you proceed.
<br/><br/>Here are a couple of bookends for you to consider:
<br/><br/>One very brute force solution contained 24 assembly language instructions (two of which were needed only to clear a flag used to signal the test script to stop), but took as many as 589814 clock cycles to run.
<br/><br/>This program had the advantage that it was very easy to write, being a direct translation of a simple high-level algorithm into assembly.
<br/><br/>By leveraging the unusual capabilities of the Hack's C-type instructions, it was possible to shave 6 instructions from the program. This may not sound like much, but because these instructions were located inside a loop, it reduced the worst-case number of clock cycles to 393212, an improvement of 33.3%.
<br/><br/>It is tempting to think that the key to making a program run quicker is to make it shorter. But it is quite common that adding instructions to a program can produce a significant improvement in execution speed. In this case, some thought about what determines how many times the program's loop executes led immediately to the addition of 18 instructions (thereby doubling the length of the program) that reduced the worst-case execution time to just 2193 clock cycles, a reduction of over 99%, even though the basic algorithm was untouched and is therefore still the same very brute force approach.
<br/><br/>Turning to a fundamentally different approach to the problem, a much more efficient solution contained 28 assembly language instructions and never required more than 334 clock cycles to execute. However, the same observation that was used to reduce the number of passes through the loop in the brute force version was then applied to this solution, resulting in 48 instructions whose worst-case performance only required 188 clock cycles.
<br/><br/>So the two extremes are 188 clock cycles versus 589814, a staggering difference of a factor of 3137 times longer.
<br/><br/><br/><br/><br/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037271Project 4 - Fill.asm: Things to consider2023-07-08T16:16:54Z2023-07-08T16:16:54ZWBahn
The Fill.asm project is open-ended in that the assignment does not specify how you are to go about achieving the desired outcome, only what that outcome needs to be: If the user presses and holds a key down long enough, eventually the entire screen will become black, while if they leave no key pressed long enough, the entire screen will become white.
<br/><br/>There are LOTS of ways to achieve this, some more elegant than others, some more efficient than others, and some more intuitive than others. But as long as those two criteria are satisfied, the solution is a valid solution.
<br/><br/>Having said that, how to we confirm that the solution is valid?
<br/><br/>This is easier said than done. There are 8192 16-bit memory cells in the SCREEN memory map, meaning 131,072 pixels on the screen. Ideally, the test script would put some keycode in the keyboard buffer (the KBD register) and then let the program run until every pixel was black. It would then put a zero in the keyboard buffer and run until every pixel became white. There are two problems with this approach. First, what if the program doesn't work properly such that the screen never does become entirely black or entirely white? At what point should the test script give up? Second, testing the entire contents of the screen is very time consuming, so how frequently should it be checked? A test script that would take hours (or years) to execute even on a well-written and correct program is useless.
<br/><br/>So the testing of Fill.asm represents a compromise.
<br/><br/>There are actually two test scripts. The first one, Fill.tst, isn't really a test script at all, it merely tells you to run your program and press a key and for you to visually confirm that the screen eventually turns all black, and then to release the key and for you to visually confirm that the screen eventually turns all white. This script should not be run on the command-line version of the CPU Emulator because it never stops. Also, the command-line version does not allow for keyboard input or screen output. The result is that the emulator will run forever without yielding any results -- this script is purely for interactive testing via the GUI version of the emulator.
<br/><br/>The second test script, FillAutomatic.tst, is an attempt to automate the testing process, but passing it does NOT mean that your program actually worked properly -- and failing it does not mean that your program didn't. Here's why.
<br/><br/>The test script performs three tests. First, it clears the keyboard buffer and then executes your script for one million clock cycles. The belief is that if your program hasn't made the screen all white by then, it likely never will. But if your program would do it in three million clock cycles, the program is technically correct, even though the test script probably declared it a failure. After the one million clock cycles, the test script checks nine specific memory addresses to see if they contain the expected values. It then repeats this process after placing a keycode in the keyboard buffer, running the program for another million clock cycles followed by checking those same specific addresses again. Finally, it clears the keyboard buffer, runs a million clock cycles, and checks those nine addresses a third time.
<br/><br/>If those nine address all contain the correct value, then the script assumes that all 8K memory addresses in the screen buffer are correct. These nine addresses were chosen to examine commonly missed pixels, as well as a few "random" locations. The belief is that it is unlikely that an incorrect program would happen to correctly set all nine of these RAM cells in all three tests. But if yours does, then the script might declare your program correct even when it isn't.
<br/><br/>A couple of final observations: It might sound like a million clock cycles is a lot, but if your program has a loop that sets the value of a single pixel on each pass, then that only allows each pass to consume an average of 7.6 clock cycles. At the other end of the spectrum, this problem can be solved with a program that requires a little over 100k clock cycles per test.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4032166Confused about CPU-external.cmp2018-06-26T06:54:41Z2018-06-26T06:54:41Zgnb03
Hi,
<br/><br/>So I was working through CPU-external.cmp by hand so I could compare what I was getting from my own CPU to what I should be getting. I was going through the assembly language provided in the comments of the file, but I found something that did not make sense.
<br/><br/>Following line 12 of the assembly, I believe that the CPU should jump to line 14(I expected the D-register to equal -1 at time when the JLT command is given). Thus, the CPU should skip line 13(@999). However in the compare file, the CPU clearly accepts @999 as you can see that ‘addressM’ is set to 999 at time 13. At the same time in the compare file, the PC jumps from 11 to 14. How can the CPU jump from 11 to 14 while taking the command from line 13?
<br/><br/>I have copied the assembly from the comments of the CMP file and pasted them below. I have also added line numbers.
<br/><br/>1 @12345
<br/>2 D=A
<br/>3 @23456
<br/>4 D=A-D
<br/>5 @1000
<br/>6 M=D
<br/>7 @1001
<br/>8 MD=D-1
<br/>9 @1000
<br/>10 D=D-M
<br/>11 @14
<br/>12 D;JLT
<br/>13 @999
<br/>14 A=A+1
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037199Hardware Simulator showing strange error message and not loading my CPU chip2023-05-16T11:02:36Z2023-05-16T11:02:36Zthedumbone
seems like my CPU chip has some bugs but the error message is not helping. it says "line 100, ainstruction has no source pin". First of all, I don't understand what does it mean and second, my code does have exactly 100 lines but that includes LOTS of comments and the 100th line is the closing parenthesis.
<p>Posted in <a href="/Project-5-f32606.html">Project 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037188Why we need ALU "feedback" in the registers? (CPU implementation)2023-05-15T06:26:38Z2023-05-15T06:26:38Zthedumbone
I don't understand the logic behind ALU "feedback" in A and D registers. why do we need it?
<p>Posted in <a href="/Project-5-f32606.html">Project 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037184need help understanding screen memory mapping2023-05-15T04:54:46Z2023-05-15T05:02:04Zstranger
please,with screen memory mapping the part that confuses me is "Set the (col % 16)*th* bit of word to 0 or 1" so if you were to do word= 32*(Row)1+(column) 2/16
<br/>therefore: 2/16=0.125 word=32+0=32
<br/>and since "col%16"=colmodulo 16 aka the remainder of col/16 you'd have to set the 125th bit of the 32nd memory address to zero or one? that obviously doesn't make sense so what am i misunderstanding.
<p>Posted in <a href="/Chapter-4-f32603.html">Chapter 4</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037141Issue with Memory.hdl2023-04-26T21:45:57Z2023-04-26T21:45:57Zsetanjan123
Hi, I am new to this forum. So I am on Project 5 and am working on the Memory.hdl implementation. The thing is I wrote the HDL and I cannot find a fault with it. However the test always fails at Line 53. Now when I Googled it , I found a few other implementations on Github that were very similar to mine and it turned out they also failed the test. So after some digging around I found their test files are different and quite a bit shorter.
<br/><br/>Is this a well known bug or something across the community? Did the tests just get updated in the past 2-3 years to cover more edge cases? Or did they just write their own test cases?
<br/><br/>Here is my implementation for reference:
<br/><br/>CHIP Memory {
<br/> IN in[16], load, address[15];
<br/> OUT out[16];
<br/><br/> PARTS:
<br/> // Put your code here:
<br/> DMux(in=load, sel=address[14], a=loadmemory, b=loadperi); // Check if normal RAM or peripherals
<br/><br/> DMux(in=loadperi, sel=address[13], a=loadscreen, b=loadkeeb); //Screen or Keyboard
<br/><br/> RAM16K(in=in, load=loadmemory, address=address[0..13], out=outram);
<br/> Screen(in=in, load=loadscreen, address=address[0..12], out=outscreen);
<br/> Keyboard(out=outkeeb);
<br/><br/><br/> Mux16(a=outscreen, b=outkeeb, sel=address[13], out=out1);
<br/> Mux16(a=outram, b=out1, sel=address[14], out=out);
<br/>}
<p>Posted in <a href="/Project-5-f32606.html">Project 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4035309Can't load .asm to CPU emulator2020-12-12T02:01:52Z2020-12-12T02:01:52ZVijay99
When I load any .asm file in the CPU emulator the instructions do not appear in the ROM column. It was working very well sometime ago when I ran some sample .asm files to know it better.
<br/><br/>
<p>Posted in <a href="/CPU-Emulator-f32607.html">CPU Emulator</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037051Ways of implementing an infinite loop in project 42023-02-02T23:41:46Z2023-02-02T23:41:46Zsunnysideup
Hi I've learned in the lecture that we should end instructions with an infinite loop like this
<br/><br/>(END)
<br/> @END
<br/> 0;JMP
<br/><br/>but while doing the project, I came to wonder if I could just omit the @END line like below,
<br/>since the A register will always be set to @END anyways,
<br/><br/>(END)
<br/> 0;JMP
<br/><br/>it works when I run the emulator but I'm curious whether this could lead to any potential problems?
<br/>thank you for your help!
<p>Posted in <a href="/Chapter-4-f32603.html">Chapter 4</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037038FillAutomatic.tst fails but Fill.asm seems to do what it's supposed to2023-01-15T13:22:42Z2023-01-15T13:22:42Zburge91
The screen goes black when any key is down, and white when no key is down. But the FillAutomatic test fails when changing to black. Am I okay to continue to the next chapter since the program does what it's supposed to do? Or should I get this test passed first? Been on it for weeks now tinkering to no avail.
<p>Posted in <a href="/Chapter-4-f32603.html">Chapter 4</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036634Jump logic2022-02-07T21:59:57Z2022-02-10T22:53:57Zbwspot
It seems like comparing J bits with NG or ZR is needed.
<br/>Also to my understanding ALU will never output ng=1 and zr=1 at the same time.
<br/><br/>My though process is like this.
<br/>Lets say I need to check for Jump JEQ where j1,j2,j3 are: 0 1 0. (case for alu output = 0)
<br/>In such scenario ALU will output:
<br/>ZR = 1 and NG = 0.
<br/><br/>I tried to AND:
<br/>And j1 and ng - if ng is 0 I have a match it with j1 bit.
<br/>And j2 and zr - if zr is 1 I have match for j2 bit.
<br/>And j3 and ng - if zr is either 0 or 1 I have no match for j3 bit resulting 0.
<br/><br/>But in testing above was failing for >0 condition so i came up with below logic just for J3 bit:
<br/>J3 zr ng truth table:
<br/>1 0 0 - 1 matches >0 so i solved for it
<br/>1 0 1 - 0
<br/>1 1 0 - 0
<br/>1 1 1 - 0
<br/><br/>J3 + !ZR + !NG
<br/><br/>Above seems to be working but when ng and zr are both 1 the output is 1 in some cases.
<br/>But alu will never output 1 for both zr and ng so would above be acceptable Jump logic solution?
<br/><br/><br/>I tried to improve above with below logic:
<br/><br/><0
<br/>//j1 +!zr + ng
<br/><br/>=0
<br/>//J2 + zr + !ng
<br/><br/><0
<br/>//J3 +!zr !ng
<br/><br/>It works but it only fails in 2 cases when zr and ng are 1 which would never be a case so technically it would work. Those cases are for checking for NOT 0 and for unconditional jump.
<br/><br/>I wonder if both of these are acceptable or i need to improve it?
<br/>Once this logic is correct i will add it to the CPU.
<br/>I hope anyone here can help me and guide me into the right direction.
<br/><br/>thx
<br/><br/>Edit: I removed source code per posting guidelines.
<br/>
<p>Posted in <a href="/Project-5-f32606.html">Project 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036936Setting A in C-instruction2022-10-30T01:25:56Z2022-10-30T01:25:56Zeatmorepies
I've correctly implemented the chips mentioned in Chapter 5. I'm still unsure if I understand the CPU chip correctly, so I am hoping to get some confirmation.
<br/><br/>Suppose we wanted to set the A register of our Hack computer to the value of D. Based on the CPU specification and a C-instruction `A=D`:
<br/>1. Since at the beginning of the instruction execution we do not have D from the ALU, our CPU would first try to set our A register to some superflous value (not from `instruction`, because the relevant bit is set to instead obtain the value from the ALU output).
<br/>2. After the second Mux, the ALU outputs the D value to the first Mux.
<br/>3. We've reached the end of our `.hdl` file, so now we are in `tock`. Our ALU output is stabilized, so we again use the relevant control bit to set the a register to the ALU output.
<br/><br/>Am I understanding this operation correctly? Is there anything I'm missing?
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036930getting out of screen bounds2022-10-27T13:48:06Z2022-10-27T13:48:06Zitamar_5250
I try to run my code. when I press for too long(or don't press for too long), i get the message:
<br/>"Destination is M but A=24577 is an illegal memory address".
<br/>The problem is I think I did handle this situation, so why isn't it working?
<br/><br/>Here is my code:
<br/><br/>//initiallize variables:
<br/>@idx_b // black index
<br/>M=0
<br/>@idx_w // white index
<br/>M=0
<br/>//loop condition:
<br/>(LOOP)
<br/>@KBD
<br/>D=M
<br/>@WHITE_COLOR
<br/>D;JEQ
<br/><br/><br/>//fill the screen in black color:
<br/>@idx_w
<br/>M=0
<br/>//check if i got to the end of the screen, if true, then return back to the beginning of the loop:
<br/>@idx_b
<br/>D=M
<br/>@KBD
<br/>D=D-A
<br/>@LOOP
<br/>D;JGE
<br/>// if i got here, i can fill the current 16 pixels:
<br/>@idx_b
<br/>D=M
<br/>@SCREEN
<br/>A=D+A
<br/>M=-1
<br/>//index+1 and return back to loop:
<br/>@idx_b
<br/>M=M+1
<br/>@LOOP
<br/>0;JMP
<br/><br/>(WHITE_COLOR)
<br/>//fill the screen in white color:
<br/>@idx_b
<br/>M=0
<br/>//check if i got to the end of the screen, if true, then return back to the beginning of the loop:
<br/>@idx_w
<br/>D=M
<br/>@KBD
<br/>D=D-A
<br/>@LOOP
<br/>D;JGE
<br/>// if i got here, i can fill the current 16 pixels:
<br/>@idx_w
<br/>D=M
<br/>@SCREEN
<br/>A=D+A
<br/>M=0
<br/>//index+1 and return back to loop:
<br/>@idx_w
<br/>M=M+1
<br/>@LOOP
<br/>0;JMP
<br/><br/><br/>// (RESETB)
<br/>// @idx_b
<br/>// M=0
<br/>// @LOOP
<br/>// 0;JMP
<br/><br/>// (RESETW)
<br/>// @idx_w
<br/>// M=0
<br/>// @LOOP
<br/>// 0;JMP
<p>Posted in <a href="/Project-4-f32605.html">Project 4</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036893Not able to finish Fill.asm2022-09-18T00:40:24Z2022-09-18T00:40:24Zwajde
been working on it for serval days now , cant see what is it that im missing here, i will be glad for some help
<br/>Thank you
<br/><br/><br/>(Loop)
<br/> //1: reset all values
<br/> @KBD
<br/> M=0
<br/> @8192 // 8192 pixels screen
<br/> D=A
<br/> @count // variables start at address 16 in Hack language
<br/> M=D // stored 8192 in count @16, RAM[16] = 8192
<br/>
<br/> //2: get the screen addres
<br/> @SCREEN
<br/> D=A
<br/> @screen //@17
<br/> M=D // address = 16384 (base address of the Hack screen)
<br/><br/> // //3: reset i = 0 // @18
<br/> // @i
<br/> // M=0
<br/><br/> //4: check color and update screen value
<br/> @color // default color is zero
<br/> M=0
<br/>
<br/>
<br/> @KBD
<br/> D=M // GET VALUE PRESESD // value will be
<br/> // anything but 0 when clicked there for
<br/> // if there a key pressed set R0 to -1
<br/> @FILL
<br/> D;JEQ // If D = 0 jump to FILL_SCREEN and fill with white
<br/>
<br/> // we didnt jump to fill screen with white
<br/> // so i update the color to black (-1) and the next presedure
<br/> // wil be fill screen
<br/> @color
<br/> M=-1 ;
<br/><br/> (FILL)
<br/> // FILL SCREEN ADDRES WITH THE COLOR
<br/> @color
<br/> D = M
<br/> @screen
<br/> A = M // writing to memory using a pointer:
<br/> M = D // RAM[address] = color (16 pixels)
<br/>
<br/>
<br/> // // increase I by one
<br/> // @i
<br/> // D=M
<br/> // D=D+1
<br/> // M=D
<br/>
<br/> @count
<br/> M=M-1 // Decrease count by one
<br/>
<br/> // check condtion if count == 0 go to end
<br/> // @count
<br/> D=M
<br/> @Loop
<br/> D;JEQ
<br/>
<br/> // update screen Pointer for the next iteration
<br/> @screen
<br/> M=M+1
<br/> // D=M
<br/> // D=D+1
<br/> // @screen
<br/> // M=D
<br/>
<br/> @FILL
<br/> 0;JMP
<br/><br/>
<br/>
<br/>
<p>Posted in <a href="/Project-4-f32605.html">Project 4</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036889where is Or16 used ?2022-08-20T06:00:35Z2022-08-20T06:00:35ZBartp
I completed all the hardware implementations without 'inventing' own chips as Or16Way.
<br/>However on checking all the chips, I found I did not use the Or16. The other chips all ended up in the Computer in the end.
<br/>Probably some of my implementations are less optimal.
<br/>Can someone let me know where he/she utilized Or16 ? Then I can have a look at it and make a probably better implementation.
<br/>Thanks!
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036847Memory chip2022-07-01T07:59:54Z2022-07-01T07:59:54Zaser58
Does HDL has if..else statement ?
<br/><br/>If not, how can I find if the In input is between 16384 to 24575 ?
<br/>
<p>Posted in <a href="/Project-5-f32606.html">Project 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036838Why does the instruction memory and data memory need to be time dependent?2022-06-21T09:41:42Z2022-06-21T09:41:42ZHighSchoolerWhoAsksHowTooMuch
In the hack CPU, the Program Counter, Instruction Memory, and Data Memory (except the screen) are time dependent.
<br/><br/>Why does the Memory need to be time-dependent if the PC, which determines what ROM instruction is run next, is time-dependent?
<br/><br/>Thank you!
<p>Posted in <a href="/Project-5-f32606.html">Project 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4035291Source code for CPU simulator?2020-12-04T04:38:03Z2020-12-04T04:38:03ZDoctorMikeReddy
I'd like the chance to create new CPU architectures, such as adding flags to the ALU, etc. However, the CPU, and other bits, are already coded as JARs and Classes. Is there a chance that some of the source could be open sourced, to allow us to make our own variants of the CPU emulator?
<br/><br/>DoctorMike
<p>Posted in <a href="/CPU-Emulator-f32607.html">CPU Emulator</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036788Hack Memory System Explanation Confusion2022-05-06T02:15:12Z2022-05-06T02:15:12Zjav4di
<b>CONTENTS DELETED</b>
<div class="weak-color">The author has deleted this message.</div>
<p>Posted in <a href="/Chapter-4-f32603.html">Chapter 4</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036768HELP: Project 5 CPU Jump?2022-04-16T10:19:55Z2022-04-16T10:19:55ZPAcmpstudent
Hello all,
<br/><br/>I'm currently working on the CPU part of project 5, and while my chip mostly seems to be working, I'm genuinely wondering if something is wrong with the CPU.tst file. As you can see, the code that it's running sets D to zero, and then runs D;JEQ. Unless I'm fundamentally misunderstanding jumps, this should lead to the program jumping - which it does. However, apparently the .tst file wasn't anticipating a jump, so I'm getting errors. Out of frustration, I did something that I <i>never</i> do, and went to look up other people's solutions on GitHub, wondering if their versions of the program were free of some error I wasn't catching, but they too broke at this line of code. Does anyone know what's going on? Thank you.
<br/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4036768/error1.png" border="0"/><br/>The line of code my chip is breaking at.
<br/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4036768/error2.png" border="0"/><br/>The expected output.
<br/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4036768/error3.png" border="0"/><br/>What my chip is doing.
<br/><br/><br/>
<p>Posted in <a href="/Project-5-f32606.html">Project 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036683Feedback on Edition 2 CPU project2022-02-22T16:57:34Z2022-02-22T16:57:34Zphayter
Re-posted here as more appropriate.
<br/><br/>This is a great project. And I have a couple suggestions.
<br/><br/>1) Decoding the j-bits for PC control is the most interesting part of this project. The j-bits have a specific pattern which helps in their efficient decoding - this is clearly part of a well thought out design. Given the book's objectives I believe it would be a good idea to point this out; that is, that a carefully designed instruction can facilitate an economic hardware implementation. Without giving away the pleasure of the project's design, an additional sentence could be added in the next to last paragraph in section 5.3.1 to point this out.
<br/>
<br/>Suggested sentence: As part of a well-designed instruction the j-bits have a specific pattern to facilitate hardware implementation.
<br/>
<br/><br/>2) I found the text in figure 5.8 misleading. The text implies that the ccccc..ccc instruction bits can be connected directly to the A register, Mux16, etc. Quoting: "...we don't specify which bits go where..." This misleading is further emphasized in the schematic which shows the ccccc....cc instruction coming in and the A register, Mux16, etc having c connections. When in reality these c-bits are not directly connected.
<br/><br/>Suggestion: simply label these A register, Mux16, etc connections with some other letter.
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036659Can't run Mult.tst: a .hdl file is expected2022-02-12T06:40:58Z2022-02-12T06:40:58Zburge91
The test file says a HDL file is expected when I run it. I have Mult.asm and Mult.hack in the same directory as Mult.tst, in the original folder, with some other programs.
<br/><br/>Any tips?
<p>Posted in <a href="/Chapter-4-f32603.html">Chapter 4</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4034432RISC/CISC Hack Architecture2020-04-18T16:10:02Z2020-04-18T16:10:02Zthatwillchaiguy
Hi all,
<br/><br/>What are the advantages/disadvantages between RISC and CISC?
<br/><br/>Also, which one of the two is our HACK architecture?
<br/><br/>Thank you!
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036646Stall states2022-02-10T00:27:13Z2022-02-10T00:27:13Zyhirshhorn
Will the HACK CPU know how to stall when loading from memory if implemented on real hardware or FPGA? Or is that an implementation detail that was trimmed off of the CPU for the purposes of the course?
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036599CPU.tst works but CPU-external.tst fails2022-01-23T13:30:28Z2022-01-23T13:30:28Zburge91
I can send you my CPU implementation. I'm not sure what the external test is for but it fails at line 35.
<br/><br/>My way of solving the CPU was some logic plus trial and error. It's about 30 lines. I'm worried that I've got a botched and incomplete solution. But I'm so pleased that I finally did it that I don't mind so much and will try to fix later. But any suggestions would be appreciated.
<br/><br/>I used normal Registers rather than AReg and DReg for the external test as I read it's for when they don't work.
<br/><br/>Suggestions?
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036597Just want to say hurray for making the CPU2022-01-23T13:15:26Z2022-01-23T13:15:26Zburge91
I gave up around 3/4 years ago because I couldn't make the CPU but I've come back and made it. I had to test and try things out a lot and spent hours on it. But wahooh!
<p>Posted in <a href="/Chapter-5-f32604.html">Chapter 5</a></p>