tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:forum-33916Nabble - Book - 1st Edition2024-03-29T00:45:50Ztag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036880Second edition, 7.4.1, p1382022-08-03T19:39:04Z2022-08-03T19:39:04ZJChristensen
The last sentence in the first paragraph on p138 says, "The translation scheme described above will cause static 5 and static 2 to be mapped on RAM addresses 16 and 17, respectively.
<br/><br/>I created Foo.vm as follows:
<br/><br/>push constant 100
<br/>push constant 200
<br/>pop static 5
<br/>pop static 2
<br/><br/>When run with the supplied VM Emulator, static 5 and static 2 are mapped on RAM addresses 21 and 18, respectively.
<br/><br/>It seems that either the text or the implementation of the emulator must be incorrect.
<br/><br/><a href="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4036880/vme.png" target="_top" rel="nofollow" link="external">vme.png</a>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036446Suggestions for improvements in the book2021-11-02T13:37:07Z2021-11-02T13:37:07Zaloha12
I have two suggestions, which may improve the book.
<br/><br/>1. It would be nice if the book would mention the fact that the CPUEmulator runs *a lot* faster if you choose "no animation". This information is especially useful for the Fill.asm project in chapter 4. I think as of now this information is only available on this forum.
<br/><br/>2. In the section describing the syntax of .asm files, it would be nice to explicitly mention that inline comments, i.e. comments in the same line as instructions, are not supported. While the current description is correct and complete, I think assuming support for inline comments may be a common mistake. This is especially important because as of now, inline comments lead to a silent failure; the program simply won't load into ROM, without providing any pointers to the source of the problem.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036735Edition 2, Chapter 8 typos with Fibonacci2022-03-18T21:10:20Z2022-03-18T21:10:20Zphayter
Top of page 168, the hyphenation introduced a typo in two places:
<br/><br/>#1
<br/>....Fibonaci-
<br/>iSeries
<br/><br/>should be:
<br/><br/>...Fibonacci-
<br/>Series
<br/><br/>#2
<br/>...Fibo-
<br/>naciiElement
<br/><br/>should be:
<br/>...Fibo-
<br/>nacciElement
<br/><br/>that is, 2 letters for c and not 2 letters for i
<br/><br/>This typo is repeated but not hyphenated further down in the second paragraph:
<br/>FibonaciiSeries
<br/>FibonaciiElement
<br/><br/>The previous page, page 167, spells these correctly.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036560Possible error in 2nd ed spec of multiway demux (p. 24)2022-01-07T13:38:34Z2022-01-07T13:38:34Zphilbangayan
There may be an error with the way the multiway demux is specified in page 24 (section 1.4) of the second edition of the book. The function reads:
<pre>
Input: in, sel[2]
Output: out
Function: if (sel==00) then {a,b,c,d} = {1,0,0,0},
else if (sel==01) then {a,b,c,d} = {0,1,0,0},
else if (sel==10) then {a,b,c,d} = {0,0,1,0},
else if (sel==11) then {a,b,c,d} = {0,0,0,1}
</pre>
But this means that no matter what the input in is, the output on one of the lines would be 1. I think the function should instead read:
<pre>
Input: in, sel[2]
Output: out
Function: if (sel==00) then {a,b,c,d} = {in,0,0,0},
else if (sel==01) then {a,b,c,d} = {0,in,0,0},
else if (sel==10) then {a,b,c,d} = {0,0,in,0},
else if (sel==11) then {a,b,c,d} = {0,0,0,in}
</pre>
This way, if the output on one of the lines will be match the input, which could be either 0 or 1. I also notice this is more consistent with what's in the first edition.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036460Chapter 5.2.4, "manipulate" memory2021-11-04T05:27:16Z2021-11-04T05:27:16Zaloha12
Chapter 5.2.4 contains the following lines:
<br/><br/>"With that in mind, when a low-level program wants to read something from the keyboard, or write something on the screen,
<br/>the program manipulates the respective memory maps of these I/O devices."
<br/><br/>I think "manipulates" is an imprecise wording here; it's definitely correct in the case of writing to the memory map of the screen,
<br/>but in the case of reading the keyboard input the keyboard memory map is only read and not influenced/changed in any way,
<br/>therefore "manipulates" is arguably wrong in this case. Maybe change this to "interacts with" or something similar? This would
<br/>keep the overall sentence structure intact, especially the fact that it starts with "keyboard" and "screen" and ends with "these I/O devices",
<br/>hinting to the reader that this behaviour generalizes to any I/O device.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036166Possible typo in 2nd Ed: 4.2.1 Background, Branching2021-07-21T19:35:23Z2021-07-21T19:35:23Zrleininger
There appears to by a minor typographical error in Chapter 4 of the 2nd Edition in Section 4.2.1, Branching: as highlighted in yellow in the following snip from the Kindle version of the book.
<br/><br/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4036166/2021-07-21_21-23-23.png" border="0"/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-40361342nd Edition: A1.3 The Expressive Power of Nand2021-07-06T06:25:08Z2021-07-06T06:25:08Zouverson
In A1.3 The Expressive Power of Nand
<br/><br/>There is a phrase:
<br/><br/>"It follows that any Boolean function can be represented by a Boolean expression containing only And, Or, and And operators."
<br/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4036134/a-1-3-the-expressive-power-of-nand.jpg" border="0"/><br/><br/>I think this was supposed to be "... only And, Or, and <b>Not</b> operators."
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4035417Should I start reading the book and doing peojects now, or wait for the 2nd edition book?2021-01-11T10:15:06Z2021-01-11T10:15:06ZVitalyR
There will be a 2nd edition of the textbook at July 2021.
<br/>Should I start now or wait?
<br/>Will the projects change a lot?
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-3814739typo in Fig 2.6? (x+1 vs x-1)2012-03-10T01:48:02Z2012-03-10T01:48:02Zkowey
The table in the Kindle edition seems to say that you compute x+1 with !(!x + 1) [nx, zy, ny, f=+, no], and conversely that you get x - 1 by taking x + 1 [zy, ny, f=+].
<br/><br/>Has that just been switched around or am I confused? (Similarly for figure 4.3)
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4032572Chapter 1 PDF, Slide 21, error in NAND table?2018-11-24T00:15:08Z2018-11-24T00:15:08Zcrazysmoove
In the Chapter 1 PDF here: <a href="https://docs.wixstatic.com/ugd/56440f_51f7dbaa5d004686a9576588088458c6.pdf" target="_top" rel="nofollow" link="external">https://docs.wixstatic.com/ugd/56440f_51f7dbaa5d004686a9576588088458c6.pdf</a><br/><br/>The NAND table has:
<br/><br/>x y Nand
<br/>0 0 1
<br/>0 1 1
<br/>1 0 1
<br/>1 1 1
<br/><br/>Shouldn't the "1" on the last row under the "Nand" column be a 0 instead?
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4032438Boolean Logic Truth Table2018-10-18T13:38:07Z2018-10-18T13:38:07Zpimaths66
In chapter 1, Truth Table Representation, there is a sentence:
<br/><br/>"For each one of the 2n possible tuples v1 ... vn (here n ¼ 3)"
<br/><br/>What exactly does this mean?
<br/><br/>I see there is x, y, z and then the output on the right.
<br/><br/>2^n , there are 3 values , what is being raised to the nth power. What is 1/4 3.
<br/><br/>Help please what is this saying?
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4032180Error on page 70 under "Screen" subsection and some unclear notation2018-06-28T14:09:31Z2018-06-28T14:09:31ZAverageOyster
Specifically the third line up from the bottom of the page. The address of RAM[16384+r*32+c/16] is incorrect, the address should read 16384+r*32+floor(c/16).
<br/><br/>I saw somewhere on this forum that in addressing situations like this, it is assumed that floor(c/16) is what is meant by c/16, but this assumption is confusing to those of us who didn't know that because the assumption is not stated anywhere in the preceding sections of the book. For a while, I thought the fraction was supposed to refer to a specific bit within a wider word. Why rely on an assumption like "c/16 means floor(c/16)" when there is a perfectly legitimate and simple way to just write the address without redefining the division operation?
<br/><br/>In a similar vein, page 70 also introduces another new notation under the assumption that the reader is already familiar with it. Every RAM address on this page is followed by a number written like (0xdddd); I now understand that this is just the address written in hexadecimal following a prefix notation commonly found in programming languages. However, for a while I was extremely confused because it was never explained that this number is just a weird way to write hexadecimal; this format just suddenly appears out of nowhere. Perhaps it would be better to introduce the "0x" notation before using it, or maybe just follow the base notation established in Chapter 2 and write the numbers in the form (dddd)_sixteen.
<br/><br/>I feel like a book that bills itself as being "completely self-contained" which "lends itself to non-CS majors" should never use notation that has not been properly introduced in the text, no matter how common that notation is among those in computer science/engineering.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-33919Known errors in the books2009-11-13T22:02:18Z2009-11-15T00:47:03ZShimon Schocken
Page 129, Figure 7.4: the rightmost and topmost arrow should read "lt" and not "it".
<br/><br/>Page 138, Figure 7.10:the VM code contains "/* */" comments while the VM specifications only allow "//" comments.
<br/><br/>Page 140, Figure 7.11: the VM code contains "/* */" comments while the VM specifications only allow "//" comments.
<br/><br/>Page 14, bottom table: the RAM addresses range for the heap should be 2048-16383.
<br/><br/>Page 220, bottom: the double quotes character (") is listed as a symbol that should be output in a special way while in actuality the need to output it into the XML file should not arise.
<br/><br/>Page 231, bottom: RPN is an acronym for "Reverse Polish Notation", unlike what is written.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4029130Chapter 9/Book Text PDF?2015-07-31T17:09:53Z2015-07-31T17:09:53Zjrd
Is it possible to get a downloadable PDF of Chapter 9 of the book?
<br/><br/>All of the previous chapters had download links, but I notice that starting on Chapter 9, the actual book text is not available for download (unless I've missed something). All that's downloadable for Chapter 9 is a summary PPT type set of graphics, but not the actual book text.
<br/><br/>Is there a download link available on the Nand2Tertis site or elsewhere?
<br/><br/>Pls let me know if anyone has info. Thanks.
<br/><br/>- JRD
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4026887Chapter 4 Destination Specification + Figure 4.42013-05-30T07:54:58Z2013-05-30T07:54:58Zp.konrad
Hi
<br/><br/>the book says:
<br/><br/>"The value computed by the comp part of the Cinstruction can be stored in several destinations, as specified by the instruction’s 3-bit dest part (see figure 4.4). The first and second d-bits code whether to store the computed value in the A register and in the D register, respectively. The third d-bit codes
<br/>whether to store the computed value in M (i.e., in Memory[A]).
<br/><br/>My understanding of this is
<br/>1. bit -> A
<br/>2. bit -> D
<br/>3. bit -> M
<br/><br/>the table in 4.4 though (and the example in binary) says:
<br/>1. bit -> A
<br/>2. bit -> M
<br/>3. bit -> D
<br/><br/>I might just be missunderstanding the written explanation... please let me know ;)
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-3153630Small errata in Ch. 12 and 132011-07-08T16:45:01Z2011-07-11T18:55:39ZBen
A couple more errata, from Chapters 12 and 13.
<br/><br/>1) pg 258, Figure 12.8a. In the line drawings, the slopes are written as dy/dx and a/b. The dy/dx is correct, but the other one should be b/a, not a/b (assuming it's written as y/x, but otherwise the dy/dx should be dx/dy).
<br/><br/>2) pg 270. Keyboard.readString is actually Keyboard.readLine in the API.
<br/><br/>3) pg 277, 2nd to last line: expect should be except.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4026415Error in VM Code on page 237?2013-03-03T20:37:48Z2013-03-03T20:37:48ZMike In Chicago
In the "Final VM Code" section on page 237 (chapter 11), it includes the following line of code:
<br/><br/>"call BankAccount.commission 2"
<br/><br/>However, in the high level code that appears on page 236, the commission method is shown to take only 1 argument.
<br/><br/>Since call functions are of the type "call <function name> <number of arguments pushed on stack>", should this actually read "call BankAccount.commission 1"?
<br/><br/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4026311The Elements of Computing Systems - Electronic version Chapters 7 - 132013-02-20T05:35:27Z2013-02-20T05:35:27ZLavaChild
Hello,
<br/><br/>I have recently purchased 'The Elements of Computing Systems' book having enjoying completing Chapter 1 using the online resources. I find benefit in both printed and electronic versions of each chapter. The printed version is wonderful to sit and read with no distractions however the electronic version is very useful when completing the projects (finding instances of words within a chapter, for example).
<br/><br/>I understand that the electronic versions is only available as an online resource for Chapters 1 - 6, unavailable for Chapters 7 - 13. I appreciate that this is likely to encourage people to purchase the book, however having done so would it be possible for you to supply me with the complete book in electronic format? I would be only too happy to 'prove' my purchase by way of a photograph or similar, should you request it.
<br/><br/>I look forward to hearing from you.
<br/><br/>Thank you.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4026247User-defined labels; Indirect addressing example (p. 60,61)2013-02-07T11:23:19Z2013-02-07T11:23:19Zgs99
Q1. User-defined labels are introduced on page 60:
<br/>ADD R2,R1,foo
<br/>Whereas “ADD,R2, and R1” symbols may be provided by the Machine Language, the symbol “foo” is not.
<br/>Shouldn’t there be a brief explanation of how “foo” comes to be recognized?
<br/>Perhaps we will not be using such labels.
<br/><br/>Q2. Indirect addressing – array example (p.61)
<br/>The book says: “the jth array entry should be physically located in a memory location that is at a displacement j from the array’s base address (assuming… that each array element uses a single word). Hence the address corresponding to the expression foo[j] can be easily calculated by adding the value of j to the value of foo.”
<br/>This is confusing.
<br/><br/>No example is provided, so I made one: foo is at 1600.
<br/>If the value of j is 0, foo[0] = 1600 + (16 * j) (16 * 0) (0) = 1600.
<br/>If the value of j is 1, foo[1] = 1600 + (16 * j) (16 * 1) (16) = 1616.
<br/>If the value of j is 2, foo[2] = 1600 + (16 * j) (16 * 2) (32) = 1632.
<br/>At this point, j + foo = (2 + 1600) = 1602, not 1632.
<br/>
<br/>In foo[j], j is an index showing which 16-bit address (element of array) should be used.
<br/>How can the index j also equal the displacement from the base address?
<br/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4025426Errata in lecture PDFs ?2012-10-25T16:46:00Z2012-10-25T16:46:00Zdlk
I see a folder of errata for the book, and for the projects, but not for the lecture PDFs; is there a place for them?
<br/><br/>In any case, in lecture\ 08\ virtual\ machine\ II.pdf, on slide 16, the mult() function shown is incorrect, since if j starts positive, it keeps getting incremented until it passes 32767 and rolls around to -32768.
<br/>j should be decremented in the loop.
<br/><br/>Also, multiplication by naive repeated addition is stoopid ;-)
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4025232missing chapters 7-132012-10-11T10:33:03Z2012-10-11T10:33:03Zfabiog
Hi, book chapters 7-13 are missing! I hope it's just temporary, otherwise can someone please upload them on a share server please? Thanks!
<br/><br/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4025285Lecture slide diagram ch 1 slide 212012-10-15T09:30:33Z2012-10-15T09:30:33ZReader
The diagram in upper left, the AND and OR gates are labeled backwards. Canonical is correct.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-3785964Chapter 1 Lecture2012-02-28T18:48:02Z2012-02-28T18:48:02Ztnfaust
Slide 21 in the Chapter 1 lecture has a typo. The upper-left diagram has the "and" & "or" switched (the "or" gate is labeled "and," and vice-versa). It confused me until I read it by shape instead of by word.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-3661681Section 8.2.32012-01-15T14:57:41Z2012-01-15T14:57:41ZThe111
"After the called function returns, the caller’s memory segments argument, local, static, this, that, and pointer are the same as before the call, and the temp segment is undefined."
<br/><br/>Shouldn't the word static be omitted from that list? If the static variables are accessible to all functions, then it is possible that the called function modified it, and it won't be the same... is that right?
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-206035Chapter 5 Errata2010-02-13T17:59:55Z2010-02-13T17:59:55ZWarren Toomey
page 98 paragraph 3:
<br/><br/>Thus, hardware architecture courses and textbooks typically evolve ->
<br/>Thus, hardware architecture courses and textbooks typically revolve
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-3254135Chapter 7, Page 1072011-08-14T12:03:24Z2011-08-14T12:03:24ZSimon
"Where segment is one of the eight segment names and index is a non-negative integer."
<br/><br/>constant is one of those eight segments but wouldn't "pop constant n" be invalid? Sorry if I missed something or it's been mentioned before.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-2371973Big- vs. Little- Endianness2011-01-29T18:14:45Z2011-01-29T18:14:45ZJacorb
I had some difficulty during the building of the Adders, and then again during the building of the CPU itself, with the Endianness of the architecture.
<br/>My problem was that the endianness was never explicitly declared. Once I figured out I was thinking backwards, I was able to work it out, but it caused a pile of pain during the CPU building.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-3120875Missing Prefix Pg. 25 ?2011-06-29T02:20:00Z2011-06-29T02:20:00ZMartin
"Multi-Way/Multi-Bit Demultiplexor An m-way n-bit demultiplexor (figure 1.11)
<br/>channels a single n-bit input into one of m possible n-bit outputs. The selection is
<br/>specified by a set of k control bits, where k ¼ log2 m.
<br/>The specific computer platform that we will build requires two variations of this
<br/>chip: A 4-way 1-bit demultiplexor and an 8-way 1-bit multiplexor, as follows."
<br/>--
<br/>"and an 8-way 1-bit multiplexor" should be demultiplexor.
<br/><br/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-1771025Hack actually a Harvard architecture (and not von Neumann per the book)?2010-10-25T17:39:03Z2010-10-25T17:39:03Zmalyn
Hello,
<br/><br/>I have a question about the architecture of the Hack computer. The Elements of Computing Systems is very consistent in describing Hack as a von Neumann machine, but to me Hack seems much more like a Harvard machine.
<br/><br/><br/>TECS describes the Hack architecture as follows:
<br/><br/>- Section 5.2.2: [The Hack CPU] expects to be connected to two separate memory modules: an instruction memory ... and a data memory.
<br/><br/>- Section 5.4: Unlike Hack, most general-purpose computers use a single address space for storing both data and instructions.
<br/><br/><br/>Per Wikipedia, the <a href="http://en.wikipedia.org/wiki/Von_Neumann_architecture" target="_top" rel="nofollow" link="external">von Neumann architecture</a> is described as follows:
<br/><br/>---
<br/>The von Neumann architecture is a design model for a stored-program digital computer that uses a central processing unit (CPU) and a single separate storage structure ("memory") to hold both instructions and data.
<br/>---
<br/><br/>That description is in conflict with much of Chapter 5, which states that Hack uses separate address spaces for Instructions and Data.
<br/><br/><br/>The <a href="http://en.wikipedia.org/wiki/Harvard_architecture" target="_top" rel="nofollow" link="external">Harvard architecture</a>, on the other hand, does seem to accurately describe Hack:
<br/><br/>---
<br/>The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data.
<br/>---
<br/><br/>The diagram at the top of that article is almost identical to figure 5.10 ("Proposed implementation of the topmost Computer chip") in TECS. As an aside, figure 5.1 is an accurate depiction of the von Neumann architecture, but figures 5.1 and 5.10 do not appear to describe the same thing (5.1 is von Neumann, 5.10 is Harvard).
<br/><br/><br/>Am I misunderstanding the von Neumann and Harvard architectures or is there something about the Hack architecture that does make it a von Neumann machine even though it appears to have separate Instruction and Data memory?
<br/><br/>Thank you for your time!
<br/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-207418Figure 7.102010-02-14T16:50:12Z2010-02-14T16:50:12ZKyle Smith
The figure for "Virtual memory segments just after the bar[2]=19 operation:" has the pointer value in index 0 when it should be in index 1.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-142865No projects directory?2010-01-28T19:13:11Z2010-01-28T19:13:11ZGreg
Hi,
<br/><br/>Love the book. But the software, as I downloaded it from the web site, doesn't seem to include a 'Projects' directory as described in the book. Nor can I find the skeletal .hdl files as described in the book. The 'builtins' directory *is* included, and I tried copying (eg.) Xor.hdl into a separate directory and working on it from there, but this doesn't seem to work either. The error message reporting from the Hardware Simulator seems somewhat limited. Did I download the wrong thing?
<br/><br/>Cheers and thanks!
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-109167Possible error in Figure 3.12010-01-04T20:26:14Z2010-01-04T20:26:14ZJonathan Katz
I'm not sure if this is a mistake or not, but anyway I found it slightly confusing. In the picture of the 1-bit register in Figure 3.1, 'in' should be selected when 'load' is set. But in Figure 1.8 of a Mux, the *bottom-most* input is selected when 'sel' is set.