CPU.hdl way over my head...

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CPU.hdl way over my head...

Hi there,
I understand & watched all the videos, but the CPU.hdl still seems way over my head.
I have spent a long time thinking about it, but I don't know what to implement or solve in which order and have hit a dead end...

From my perspective this task is not for real IT-beginners or perhaps I have gotten too old... but I would very much like to fight through this obstacle and complete the course!

As I may not post code, I will try to describe what my code does resp. what I have produced so far:

- I think, I need to negate the opcode bit, because of the first mux selection (otherweise sel=1 would select the instruction input).
- The first mux chooses between the ALU-output and the input instruction, using the negated opcode as selector and outputs mux1out.
- The ARegister gets the input from the first mux, I don't know what to put into "load" and it outputs Aregout.
- The second mux takes in either the Aregout or a new value from inM, I don't know what to put in sel here, and it outputs mux2out.
- My PC counter takes in Aregout, loads some bit (maybe "d1" .. ?), I also set inc=true, as I believe this would be the default behavior, as long as it musn't reset to 0 or jump somewhere, reset receives the input reset, and outputs pc.
- The DRegister takes in the ALU-output, loads some bit (maybe "d2" .. ?), and outputs Dregout.
- The ALU takes in Dregout for x and mux2out for y, uses the bits from instruction pos. 11 to 6 for its input control bits and emits aluout, zr=?? and ng=?? and I added another output outM.

That's all I have, it's not much ... :(

Beyond presuming d1 is fed to the load bit of the PC and d2 is fed to the load bit of the Dregister, I remain rather clueless...

I have not even thought about the jumping and the zr & ng bits, as I have no idea how to go about that.

I wonder, if there might be someone willing to have a look at my hdl & talk me through this task more comprehensively?
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Re: CPU.hdl way over my head...

Keep in mind that you control which input of a mux each signal goes to. So if you want Signal A to be selected when a particular control bit is a 1, route Signal A to the input of the mux that is selected when the select input is a 1.

For each control signal in the CPU you just need to ask yourself under what conditions does that signal need to be HI, under what conditions that that signal need to be LO. For any other conditions, it doesn't matter.

You need to consider both types of instructions (A-type and C-type).

So, for instance, the load signal for the D-register
A-type: MUST be LO
C-type: MUST be HI if d2 is HI, MUST be LO if d2 is LO

Now you just need to figure out what circuit will implement this logic.