Need more context. What, specifically, in the material are you referring to?
The hardware simulator operates as a fully-synchronous state machine, thus the value captured by a DFF on the rising edge of the clock is the value that was present as a result of the prior clock cycle. The value associated with the current clock cycle does appear at the input until after the DFF is no longer sensitive to it.
Before I talk about the circuit you show, be aware that the Hardware Simulator contained with the Nand-2-Tetris tools can't simulate that circuit because all of the clocked elements implicitly use a single clock signal whereas your circuit uses two clock signals.
I'm assuming that the line after your clock signal is the D signal -- the label looks more like an 'O', but that doesn't make sense.
Where is your D signal coming from? You have it changing on both the rising and the falling edges of the clock, so it can't be coming from another DFF. It could be using combinatorial logic to combine a signal from a DFF clocked by CLK and one clocked by /CLK. In either case, when it changes it will be doing so in response to the clock changing and that means that there will be a delay between the clock that causes the change and when the D signal actually changes. As a result, your first DFF will not see the change in D in time to respond to it on the present clock signal.
To see this more clearly, it is common to include a slight offset in the timing diagram to show that the actual changes in signals occur slightly after the clock edge. You don't have to do that, but you need to remember that the DFF is responding to what the signals were BEFORE the clock edge, because they don't change in time for them to respond to what they are after it (or, if they do, it is because you are violating the setup and hold time requirements for the DFF, which require that the input signal be static starting a little bit before the clock edge until a little bit after the clock edge).