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 Ok, this makes a lot more sense.  Thank you for that clarification. Oh by the way I just realized I can simplify the Add4 program above drastically.  I worked some more on the algebra and then laughed at what I was doing.  I actually recalculate  previous carry pins when they are already available.  With your reply and my corrected math I can now understand the elegance of this method.  I'll post an update version. CHIP Add4 {     IN a, b, c0;     OUT out, carry;     PARTS:     //Put your code here.     PFA(a=a, b=b, c=c0, s=out, g=g0, p=p0);     //C1 = g0+p0c0     And(a=p0, b=c0, out=pand1);     Or(a=pand1, b=g0, out=c1);     PFA(a=a, b=b, c=c1, s=out, g=g1, p=p1);         //C2 = g1 + p1g0 + p1p0c0 --> g1 + p1(g0+p0c0) --> g1 + p1c1             And(a=p1, b=c1, out=pand2);     Or(a=g1, b=pand2, out=c2);         PFA(a=a, b=b, c=c2, s=out, g=g2, p=p2);           //C3 = g2 + p2g1 + p2p1g0 + p2p1p0c0 --> g2+p2(g1+p1(g0+p0c0)) --> g2+p2c2             And(a=p2, b=c2, out=pand3);     Or(a=g2, b=pand3, out=c3);         PFA(a=a, b=b, c=c3, s=out, g=g3, p=p3);     //c4 = g3 + p3g2 + p2p3g1 + p1p2p3g0 + p0p1p2p3c0         And(a=p3, b=c3, out=pand4);     Or(a=g3, b=pand4, out=carry); }
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 Administrator In reply to this post by Shjanzey If you are interested in other types of adder optimization, check out this post on Carry Select Adders--Mark
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 Administrator Jaytron wrote Has anyone had any success implementing a full 16 bit carry lookahead adder?  I've successfully implemented the 4-bit carry lookahead adder in .hdl code as visualized here: http://en.wikipedia.org/wiki/Lookahead_Carry_Unit  but when I attempt to scale the chip up to a 16-bit lookahead carry unit the Nand2Tetris hardware simulator gives me the error that I have a "circle in my parts connection". I'm assuming that you are trying to implement the second figure on the Wiki page you referenced. You are running into a limitation of the Hardware Simulator. It sees that there are outputs p4 and g4 from the 4-bit CLA adder that connect to the 16-bit CLA chip, and the C4 output from the 16-bit CLA that connects back to the same 4-bit CLA adder. It doesn't analyze the internals of the CLA adder so it doesn't know that the C4 input doesn't affect the p4 and g4 outputs. A quick and dirty kludge is to use two CLA adders for each 4-bit group. One to generate the p and g and the other to add A, B and C. From my CLAadd16.hdl: ``` ClaAdd4(a=a[0..3], b=b[0..3], c=c, sum=out[0..3]); ClaAdd4(a=a[0..3], b=b[0..3], g=g0, p=p0); ```(There's a comment in my HDL explaining this kludge. The comment is longer than the implementation!) If you want to explore more complicated logic I highly recommend Logisim, a fairly powerful schematic-based logic simulator. --Mark