tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:forum-32595Nabble - Chapter 32024-03-28T16:51:55Z{long-desc}<b>Please read <a href="http://tecs-questions-and-answers-forum.32033.n3.nabble.com/Hardware-Construction-Survival-Kit-tp3385741p3385741.html" target="_top" rel="nofollow" link="external">The Hardware Construction Survival Kit</a> for answers to common questions and other useful information.</b>{/long-desc}tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037610The currently included PC.hdl stub file has errors2024-02-26T12:54:35Z2024-02-26T12:54:35ZMBoffin
The current PC.hdl stub file in the Nand2tetris Software Suite Version 2.7 download has parentheses for the in and out bus widths, but they should be square brackets.
<br/><br/>If you don't mind me asking, what happened to these project files? It's a mess. I've run in multiple errors in the latest version of these project files. It seems like a lot of changes were made recently and then not tested at all to make sure they actually work.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037376Confused about total memory allocation2023-09-23T01:30:23Z2023-09-23T01:30:23Ztxxnano
Greetings.
<br/><br/>I've encountered an architectural doubt I'd like to understand in greater depth. I managed to get in place, and this is just for the sake of complete understanding. Once resolved, I can move ahead with Chapter 5
<br/><br/>Hack computer architecture allows an addressable memory space of approximately 64KB (16-bit architecture). However, I've noticed that we've allocated only 2^15 addresses for both ROM and RAM.
<br/><br/>1. Is this allocation strategy a deliberate design choice, or is it a characteristic inherent to this specific CPU architecture where ROM and RAM maintain a 1:1 address ratio? (e.g: 2^15 for RAM + 2^15 for ROM)
<br/>2. Why the decision of a 15-bit address bus and not a 16-bit one?
<br/>3. What are the actual memory specifications of the Hack (if possible to answer)?
<br/><br/>Best regards
<br/><br/>PS: sorry for the three-question post, but I assumed they were all related.
<br/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037368Question about DFF chip and Clock2023-09-20T09:57:25Z2023-09-20T09:57:25ZAdam
Hello - with the DFF chip, when exactly does changing the input and the output registering it occur with regards to the clock cycle 0 0+ 1 1+ etc.
<br/><br/>For example, if the time is 0 and I set Value=1, then out will change to 1 when the time is 1.
<br/><br/>However, if the time is 0+ and I set Value=1, then out will change to 1 only when the time is 2.
<br/><br/>In other words, it seems the n+ times don't really do anything?
<br/><br/>Relating to this - how does the 0 0+ 1 1+ etc. format correspond with the 0 1 0 1 0 1 etc. format given in the book (second edition) (I assume just n is 0 and n+ is 1?), and how do these 0s and 1s correspond to a time 't' as used in the API for chips such as the DFF. I.e., we say the DFF chip has the abstraction out[t]=in[t-1], but which t is this referring to? The n or n+? Or both? And if both... how?
<br/><br/>Any help would be appreciated. Thanks!
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037330How to code this design ?2023-08-23T10:25:40Z2023-09-01T10:45:37ZXu Xian
<b>CONTENTS DELETED</b>
<div class="weak-color">The author has deleted this message.</div>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037221Ram82023-06-19T10:20:49Z2023-06-22T11:50:07Zron2308
Hi, I would be grateful for you help. I thought I have figured out the right code, but it is not the case. Internal pins are created but not the required outcome.
<br/><br/>My code is a follows:
<br/> <code snipped><br/> Mux8Way16(a=out1,b=out2,c=out3,d=out4,e=out5,f=out6,g=out7,h=out8,sel=address,out=out);
<br/>
<br/>Please help me to figure out what is wrong.
<br/>Sincerely, Ron
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4035817Why is there no clock in the Hack Computer Architechture?2021-03-10T14:44:04Z2021-03-10T14:44:04Zmotty
Hi,
<br/><br/>I was wondering, why does the course not include the clock when discussing the Hack Computer architecture? From what I understood, the clock is a key component of a sequential computer, such as the Hack machine undoubtedly is....
<br/><br/>I also feel that I lack a truly solid understanding of clocks / sequenitial logic, and I was hoping that actually building a clock and integrating it into the computer would help.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4029322How the feedback is evaluated internally in BIT2015-11-13T11:01:38Z2015-11-13T11:01:38ZThorvald
I understand that to load, or recall, a bit you need the diagramof Fig. 3.1. What I still does not understand is what happens behind the curtain. My implementation is
<br/><br/> Mux(a=outDFF, b=in, sel=load, out=inDFF);
<br/> DFF(in=inDFF, out=outDFF, out=out);
<br/><br/>(Sorry for posting the answer, but it has to be done so I can work out my question).
<br/><br/>So what happens at the beginning is that it is evaluated the mux gate, but c'mon, we don't have an initial value in outDFF, so how is this value taken into account???
<br/><br/>After that, it just go looping around this two gates, but how this is done? I mean, I would like to see a for or while loop to execute those gates a number of t-times, right?
<br/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4033496Struggling with Program Counter (PC)2019-08-17T00:39:48Z2019-08-17T00:39:48ZMultiplexorMan
I'm struggling hard with the PC. It solution seems just out of reach.
<br/><br/> Mux16(a=in, b=false, sel=reset, out=q);
<br/> Or(a=reset, b=load, out=q2);
<br/> Register(in=q, load=q2, out=q3);
<br/> Mux16(a=q3, b=q6, sel=inc, out=q4);
<br/> Register(in=q4, load=true, out=q5, out=out);
<br/> Inc16(in=q5, out=q6);
<br/><br/>This setup obviously fails because when inc=1 the load command is by passed. I feel like these posts hold the key I just haven't been able to put the puzzle pieces together.
<br/><br/>Start Here:
<br/><a href="http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/PC-struggle-td4028870.html" target="_top" rel="nofollow" link="external">http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/PC-struggle-td4028870.html</a><br/>Hint: If you connect a Register's load to true it turns the Register into a 16-bit DFF.
<br/><br/>Then you can make PC like you made bit Bit, except that the feedback wire is replaced with a circuit that computes the next value for the PC.
<br/><br/>Also, in hardware it is often easier to generate all the options you might need and select the one that's required by the current control values. Think about handling the f bit in the ALU, but in this case there are more options.
<br/>
<br/>Then This:
<br/><a href="http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/PC-Counter-td687060.html" target="_top" rel="nofollow" link="external">http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/PC-Counter-td687060.html</a><br/>note that the order of the if statements and the order of your circuitry are related
<br/>Chapter 3 has the remedy to your question. You can use one of the other chips in the chapter to control and recall different states of the counter. Hopefully this helps.
<br/>
<br/>Interesting:
<br/><a href="http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/PC-Counter-td4030223.html" target="_top" rel="nofollow" link="external">http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/PC-Counter-td4030223.html</a><br/>Just an update/FYI I actually did figure this out after reading another comment of yours! My logic was flawed in the assumption that we only wanted the register's load bit to be 1 when we load from "in". I hope this isn't too much of a hint to others looking to solve this the "simple way" but we actually want the register's load bit to be true any time there is an operation requiring a state change in the register. From there it was a simple matter of combinational logic to construct what constitutes a state change - and voila!
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036576what is wrong with my bit register?2022-01-16T22:11:52Z2022-01-16T22:11:52ZPeste_Bubonica
<br/>idk why it keeps me giving compare error
<br/><br/> PARTS:
<br/> Mux(b=dffout, a=in, out=muxout);
<br/> DFF(in=muxout, out=dffout);
<br/> Not(in=dffout, out=notnot);
<br/> Not(in=notnot, out=out);
<br/><br/>(I put two not gate together because I don't know how to use the chip output as input)
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036551What is a address?2022-01-05T13:28:06Z2022-01-05T13:53:07ZDan1984mor2017
I am looking at page 49 of the book The elements of computing systems. It shows a register and after a register the Ram. I am confused what an address is. Could you explain to me what a address is? What does it do?
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036532What is this?2021-12-26T14:12:31Z2021-12-26T14:12:31ZDan1984mor2017
I was looking at the pdf from nand2tetris part three I think and I noticed this. So I created it, but I am unsure what it is exatly. Can you give me an idea?<img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4036532/frdfgads.jpg" border="0"/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036445Initial value of DFF2021-11-02T12:38:55Z2021-11-02T12:38:55Zbikal
It is said that DFF out parameter outputs the previous value (t-1). What is the value of DFF at time 0? Undefined?
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4036278Question about Figure 3.2, Page 48, Second Edition of the book2021-08-24T13:14:17Z2021-08-24T13:14:17Zcharleszzx
<img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4036278/f32.jpg" border="0"/><br/>When studying Figure 3.2, Page 48, Second Edition of the book, I can't understand one particular part of the diagram circled red. If we probe at the transition between Cycle 3 and 4, input and output signals are both 1. However, since the picture shows a NOT gate, shouldn't the input and output signal have opposite values? Thanks for the help!
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4033903Stuck on PC2019-11-20T13:08:33Z2019-11-20T13:08:33Zmwy
Here is what I have tried so far but it seems to be stuck on line 4:
<br/><br/><br/>```
<br/>/**
<br/> * A 16-bit counter with load and reset control bits.
<br/> * if (reset[t] == 1) out[t+1] = 0
<br/> * else if (load[t] == 1) out[t+1] = in[t]
<br/> * else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
<br/> * else out[t+1] = out[t]
<br/> */
<br/><br/>CHIP PC{
<br/> IN in[16], load, inc, reset;
<br/> OUT out[16];
<br/><br/> PARTS:
<br/><br/><br/><br/> Mux16(a=in, b=false, sel=reset, out=outa);
<br/><br/> Register(in=outa, load=load, out=regout);
<br/><br/> Mux16(a=outa, b=regout, sel=load, out=loadout);
<br/><br/> Inc16(in=regout, out=reginc);
<br/><br/><br/><br/> Mux16(a=loadout, b=reginc, sel=inc, out=out);
<br/><br/>}```
<br/><br/><br/>I am still trying to figure out what I am doing wrong. Any pointers? Some guidance? I see that there are answers on the Internet, but I am trying to figure it on my own.
<br/><br/>All help is really appreciated.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4035837RAM64 Line27, a pin name is expected2021-03-15T05:21:37Z2021-03-15T05:21:37ZLeontocephaline
Hi, I encountered this troubleshooting for no apparent reason. I checked numerous times and can find no illegal or missing pin name. Please help me!
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM64.hdl
/**
* Memory of 64 registers, each 16 bit-wide. Out holds the value
* stored at the memory location specified by address. If load==1, then
* the in value is loaded into the memory location specified by address
* (the loaded value will be emitted to out from the next time step onward).
*/
CHIP RAM64 {
IN in[16], load, address[6];
OUT out[16];
PARTS:
// Put your code here:
DMux8Way(in=load, sel=address[3..5], a=q1, b=q2, c=q3, d=q4, e=q5, f=q6, g=q7, h=q8);
RAM8(in=in, load=q1, address=address[0..2], out=w1,);
RAM8(in=in, load=q2, address=address[0..2], out=w2,);
RAM8(in=in, load=q3, address=address[0..2], out=w3,);
RAM8(in=in, load=q4, address=address[0..2], out=w4,);
RAM8(in=in, load=q5, address=address[0..2], out=w5,);
RAM8(in=in, load=q6, address=address[0..2], out=w6,);
RAM8(in=in, load=q7, address=address[0..2], out=w7,);
RAM8(in=in, load=q8, address=address[0..2], out=w8,);
Mux8Way16(a=w1, b=w2, c=w3, d=w4, e=w5, f=w6, g=w7, h=w8, sel=address[3..5], out=out);
}
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4035311more thinking related to RAM82020-12-12T18:16:05Z2020-12-12T18:16:05Zlllllllalalala
As we all know, we can achieve RAM8 by inputting the address we want to store. But if I don't want to input the address myself, which means the first number will be stored automatically in the 0 position and the second number will be stored automatically in the 1 position without inputting the address. So, how can I achieve this, do I need to write some chips myself? Thank you.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4035201"sub bus of an internal node may not be used" Error Considered Annoying2020-11-06T14:18:08Z2020-11-06T15:37:50ZPaganini
<pre>
CHIP DFF16 {
IN in[16];
OUT out[16];
PARTS:
DFF(in=in[0],out=out[0]);
DFF(in=in[1],out=out[1]);
DFF(in=in[2],out=out[2]);
DFF(in=in[3],out=out[3]);
DFF(in=in[4],out=out[4]);
DFF(in=in[5],out=out[5]);
DFF(in=in[6],out=out[6]);
DFF(in=in[7],out=out[7]);
DFF(in=in[8],out=out[8]);
DFF(in=in[9],out=out[9]);
DFF(in=in[10],out=out[10]);
DFF(in=in[11],out=out[11]);
DFF(in=in[12],out=out[12]);
DFF(in=in[13],out=out[13]);
DFF(in=in[14],out=out[14]);
DFF(in=in[15],out=out[15]);
}
CHIP Register16 {
IN in[16],load;
OUT out[16];
PARTS:
DFF16(in=MuxOut,out=MuxInA, out=out);
Mux16(a=MuxInA,b=in,sel=load,out=MuxOut);
}
</pre><br/><img class='smiley' src='/images/smiley/anim_rules.gif' /><img class='smiley' src='/images/smiley/anim_blbl.gif' /><br/><br/>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4035166Creating a 16bit pc with 2 8bit registers2020-10-26T11:24:19Z2020-10-26T11:24:19ZAnon
Hi, i have been asked to make a pc using 2 8bit registers in this format
<br/>Register(in=cout, out=out[0..7], out=feedback, load=true);
<br/>Register(in=cout, out=out[8..15], out=feedback, load=true);
<br/>I have been using Inc16 and Mux16, but cannot find a way to make those components work with the 8 bit registers.
<br/>Any help would be appriciated. Thanks
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4035028RAM16K2020-08-20T19:00:25Z2020-08-20T19:00:25ZZorro
Why the Hack has 16K RAM instead of 32K? To make sure, we are not falling asleep, during copy&paste... <img class='smiley' src='/images/smiley/anim_blbl.gif' />
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4034798Question about the different ways to implement PC.hdl2020-06-29T05:46:09Z2020-06-29T05:46:09ZSandu2000
The way I implement the PC.hdl chip is by doing something similar to what is done <a href="http://people.duke.edu/~nts9/logicgates/PC.hdl" target="_top" rel="nofollow" link="external">here</a>. The only difference being I didn't specify the <b><i>a</i></b> input in the first Mux gate <b>[ Mux16(b=incrementVAl,sel=inc,out=IncrementCond) ]</b> and I didn't keep the load bit of the register as true. So basically I used OR gate to check if any of the inc, reset or load bit were 1. If not, the register doesn't load anything. Is this unnecessary? Wouldn't it be inefficient energy wise to load data into the register when it's not required?
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4034557About RAM82020-05-03T10:02:05Z2020-05-03T10:02:05Zkingofbuffs
Hello everyone.
<br/><br/>So I have been working my way through chapter 3. For RAM8 I I thought 1 demultiplexor, 1 multiplexor and 8 registers would be solve the problem.
<br/><br/>DMux would take the input and the address and load the data into a certain register, and Mux would take the address and output it.
<br/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4034557/Untitled.png" border="0"/><br/><br/>Only problem is, unless I am missing something, there's no 16 bit DMux we have created. So my solution does not work, since the input is 16 bit.
<br/><br/>What am I missing? I feel like this is the correct approach.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4034529RAM2020-05-01T13:19:41Z2020-05-01T13:19:41Zalldp19
I am watching the video lectures and I am confused about these two statements, 'At any given point of time only one register in the RAM is selected' and 'every register can be accessed at the same time instantaneously'. This is from Unit 3.3 Memory.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4034340Why we need the DFF to build the Register2020-03-25T22:55:54Z2020-03-25T22:55:54Zgeraldli
In this chapter. It says we can use DFF to construct a 1-bit register.
<br/><br/>The final circuit has input(in, load) and output(out). It’s easy to be implemented
<br/><br/>My question is, why do we need DFF to construct the 1-bit register?
<br/>As far As I know, the dff works depending on clock pulse.
<br/><br/>However, it’s possible to construct a 1-bit register <b>without the clock input</b>(I actually simulate this and it works. But I don’t know how to upload an screenshot here). It works under the same rules:
<br/>if load==1 then out=in
<br/>if load==0 then out is unchanged
<br/><br/>It seems the clock pulse is unnecessary if all we want is a simple register. The DFF with clock is much more complex.
<br/><br/>Can any one help to explain the reason of using clock-based circuit here?
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4034241address width in RAM2020-02-22T13:48:21Z2020-02-22T13:48:21Zkawakami
Why the "address" array width in RAMn is log2(n)?
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4028053Chapter 3 Terminology2014-04-27T23:59:16Z2014-04-27T23:59:16Zismithers
Hi, I'm working my way through chapter 3 and I wanted to ask about the terminology of bit and Bit which appear to be used to reference different things. A bit with a lowercase 'b' refers to the definition I'm accustomed to, which is an atomic value of information in computing. But then later there are figures in the book, such as 3.1 and 3.2 that have items labelled as Bit with an uppercase 'B'. These seem to refer to a part of a chip - is this just a lexical form in the book, or are there bits and Bits and they are different?
<br/><br/>Also I'm confused about figure 3.1 and the text in the paragraph below that references it. It says that the right-most image is the correct implementation as it uses a Mux chip. However it says that if we wish to start storing a new value, we can put the value into the in pin, and feed the selector pin with a value of 1. On page 21 the Mux diagram (and in fact my implementation) says that the the selector pin with a value of 1, will feed the input from pin b through to the out pin. Why in 3.1 does it feed what looks like pin a through to the out pin?
<br/><br/>The only thing I can think of is that 3.1 has a Mux chip but show from a different perspective - ie the underside. I don't really think that is the answer, but it's all I can think of because on page 21 the selector pin is shown on the bottom of the diagram, but in 3.1 its on the top. That would effectively reverse the a and b pin positions. Small thing, but I was just trying to be thorough and make sure I'm following what I've learned in the prior chapters.
<br/><br/>Thanks!
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4033934RAM efficiency2019-11-24T13:09:43Z2019-11-24T13:09:43ZDaniel
<br/><br/>I have implemented the RAM in the way that I think is suggested by the conferences and the chips previously developed. Essentially:
<br/><br/>- DMux the load flag.
<br/>- Probe each inferior level RAM or register / read and, if required, rewrite the addressed register.
<br/>- Mux the output.
<br/><br/>But this implementation seems to me very inefficient, because for each read or write operation, we need to probe all the registers in the RAM (16K). That seems to be because Mux and DMux operate with contents, not with instructions, so we can not just route an instruction to read or write to a specified register. Is this so or am I missing something?
<br/><br/>Even if it has to be like that in the Hack computer, I presume it is not like that in real computers. Am I right? How can this be achieved?
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4033733PC Error2019-10-05T20:29:02Z2019-10-06T12:05:56ZMike2345
<b>CONTENTS DELETED</b>
<div class="weak-color">The author has deleted this message.</div>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4033730Ram8 Error2019-10-05T16:19:13Z2019-10-06T12:06:30ZMike2345
<b>CONTENTS DELETED</b>
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tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4033436Can't grasp DFF output2019-07-30T06:55:29Z2019-07-30T06:55:29ZHenoktes722
How could the output of DFF be in(t-1) instead in(t)? I know how latches and D, T, JK flip flops work.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4033386I'm working on my last chip in chapter/week 3: the PC chip2019-07-14T06:57:07Z2019-07-14T06:57:07Zouverson
I'm working on my last chip in chapter/week 3: the PC chip
<br/><br/>I thought I had the implementation solved but am getting an error. I decided to compare my output with the compare file, and noticed something that didn't look right:
<br/><br/><a href="https://www.screencast.com/t/oK0UiI3KCw" target="_top" rel="nofollow" link="external">https://www.screencast.com/t/oK0UiI3KCw</a>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4026329Is the diagram for 'bit' on page 43 the wrong way around?2013-02-21T14:31:28Z2013-02-21T14:31:28ZJeroen
The moment I came across the 'bit' diagram on page 43 (chapter 3) it struck me as incorrect. As no one has mentioned it I am probable wrong, but according to page 21 (chapter 1) on a Mux a is the top pin and b is the bottom pin. When sel is '0' then out = a, when sel = '1' then out = b.
<br/><br/>If we apply that logic to the 'bit' diagram then setting load to '1' will return te stored value and not load the value specified in 'in'.
<br/><br/>I verified my logic with the hardware simulator.
<br/><br/>Please tell me why I am wrong <img class='smiley' src='/images/smiley/anim_confused.gif' />
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-2974049Program Counter Implementation2011-05-22T22:05:40Z2011-05-22T22:05:40ZZebo
I keep getting a comparison failure at line 9 with my implementation that seems perfectly fine. All the internal pins seem to be giving what I need but I think that I need one more clock delay. However, when I try remedy this by adding another register then I get a comparison failure at line 5.
<br/><br/>Here is the chip:
<br/><br/>CHIP PC {
<br/><br/> IN in[16], load, inc, reset;
<br/> OUT out[16];
<br/><br/> PARTS:
<br/> Mux16(a=new, b=in, sel=load, out=out1);
<br/> Mux16(a=false, b[1..15]=false, b[0]=true, sel=inc, out=out2);
<br/> Add16(a=out1, b=out2, out=out3);
<br/> Mux16(a=out3, b=false, sel=reset, out=out4);
<br/> Register(in=out4, load=true, out=new, out=out);
<br/>}
<br/><br/>Any general advice?
<br/><br/>By the way, thank you Mark for your help in my other 2 threads, that helped me out a ton.
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4025254RAM642012-10-13T03:18:38Z2012-10-13T03:18:38Zh4l0
Hi all.
<br/><br/>I have got to the RAM64 and need a little bit of a nudge in the right direction. I have had no troubles until now but can't get my head around using the RAM8 to build the RAM64.
<br/><br/>Thanks for any help.
<br/><br/>h4l0
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4033046Have I found a bug in the HardwareSimulator ? (Probably not)2019-04-01T06:16:40Z2019-04-01T06:16:40ZLozminda
Here's my code for RAM8
<br/>1 DMux8Way(in=load, sel[0..2]=address[0..2], a=l0, b=l1, c=l2, d=l3, e=l4, f=l5, g=l6, h=l7);
<br/>2 RAM8(in=in, load=l0,address[0..2]=address[3..5],out=o0);
<br/>3 RAM8(in=in, load=l1,address[0..2]=address[3..5],out=o1);
<br/>4 RAM8(in=in, load=l2,address[0..2]=address[3..5],out=o2);
<br/>5 RAM8(in=in, load=l3,address[0..2]=address[3..5],out=o3);
<br/>6 RAM8(in=in, load=l4,address[0..2]=address[3..5],out=o4);
<br/>7 RAM8(in=in, load=l5,address[0..2]=address[3..5],out=o5);
<br/>8 RAM8(in=in, load=l6,address[0..2]=address[3..5],out=o6);
<br/>9 RAM8(in=in, load=l7,address[0..2]=address[3..5],out=o7);
<br/>10 Mux8Way16(a=o0, b=o1, c=o2, d=o3, e=o4, f=o5, g=o6, h=o7, sel[0..2]=address[0..2], out=out);
<br/><br/>(I've put the line numbers in to help with the following)
<br/><br/>I run it through the HS (HardwareSimulator) and according to it, my chip is fine. I wasn't completely sure i'd wired it correctly so just to look for false positives as it were i changed line 2 to
<br/>RAM8(in=in, load=l0,address[0..2]=address[0..2],out=o0); (The second address is [0..2] not [3..5])
<br/><br/>And the HS again completed the test script with no errors
<br/>so i changed subsequent lines until i had this
<br/><br/>2 RAM8(in=in, load=l0,address[0..2]=address[0..2],out=o0);
<br/>3 RAM8(in=in, load=l1,address[0..2]=address[0..2],out=o1);
<br/>4 RAM8(in=in, load=l2,address[0..2]=address[0..2],out=o2);
<br/>5 RAM8(in=in, load=l3,address[0..2]=address[0..2],out=o3);
<br/>6 RAM8(in=in, load=l4,address[0..2]=address[0..2],out=o4);
<br/>7 RAM8(in=in, load=l5,address[0..2]=address[0..2],out=o5);
<br/>8 RAM8(in=in, load=l6,address[0..2]=address[3..5],out=o6);
<br/>9 RAM8(in=in, load=l7,address[0..2]=address[3..5],out=o7);
<br/><br/>still no errors from the HS. It was only when i'd changed all but one did i finally get a comparison error.
<br/><br/>Any thoughts anyone ?
<br/>All the best to my fellow N2Ters, have a good day!
<br/>Lozminda
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4032821Confusion about ticks and tocks2019-02-02T02:23:43Z2019-02-02T02:23:43ZGreemngreek
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