# Comparison Failure for And or Or gates

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## Comparison Failure for And or Or gates

 Good Day; For a while now, I have been stuck on this And and Or chips in hdl. I have written the truth tables and have also drawn the gates; and I was able to figure out the combination of gates I need to use to implement each of them. However, for hours now, I have been stuck. The simulator keeps outputting a 'comparison failure error' message. I know for definite that something is inherently wrong with my hdls, but I could not identify the glitch. The following is my hdl codes for both And and Or gates. Please assist! // This file is part of www.nand2tetris.org // and the book "The Elements of Computing Systems" // by Nisan and Schocken, MIT Press. // File name: projects/01/And.hdl /**  * And gate:  * out = 1 if (a == 1 and b == 1)  *       0 otherwise  */ CHIP And {     IN a, b;     OUT out;     PARTS:     // Put your code here:         Not (in=a, out=nota);         Not (in=b, out=notb);         Nand (a=a, b=nota, out=x);         Nand (a=notb, b=x, out=out);         } // This file is part of www.nand2tetris.org // and the book "The Elements of Computing Systems" // by Nisan and Schocken, MIT Press. // File name: projects/01/Or.hdl  /**  * Or gate:  * out = 1 if (a == 1 or b == 1)  *       0 otherwise  */ CHIP Or {     IN a, b;     OUT out;     PARTS:     // Put your code here:         Not (in=a, out=nota);         Not (in=b, out=notb);         And (a=a, b=notb, out=x);         And (a=nota, b=b, out=y);         And (a=x, b=y, out=out);         }
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## Re: Comparison Failure for And or Or gates

 Administrator In your And gate code, you have: Nand (a=a, b=nota, out=x); What does the truth table for that look like? Since 'nota' is always the opposite of 'a', one of them will be HI and the other will be LO, right? The definition of the Nand gate says that the output is LO if and only if both of the inputs are HI, which can never happen in this case, so the output of this, namely x, will always be HI. The end result is that you have implemented a very complicated buffer whose output is whatever the 'b' input happens to be. Keep in mind what "Nand" stands for -- Not And. What do we know about a double negative, namely Not Not?
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## Re: Comparison Failure for And or Or gates

 Thank you! Your detailed explanation is truly educative. However, I would like to know what 'HI' and 'LO' really means.
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## Re: Comparison Failure for And or Or gates

 Administrator HI and LO are just common names for logical constants. Other common names are "true" and "false", as well as "1" and "0".
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## Re: Comparison Failure for And or Or gates

 Alright Thanks a lot. But could you please shed more light to this And gate issue. I have tried all my possible best and then realized that Nand gate can't be used in the implementation of the And chip as shown above. As a matter of fact, Not is the only chip I have been able to successfully implement so far. After your explanation, I re-dissect the combination of Not and Nand gates to produce And therefrom; but i realized that it is somewhat impossible. Normally, The two Nots implementation I have in the parts are given me the expected result for the first three rows of the And gate. Since Nand is the opposite of And, I am not getting the correct value in the last row of the And gate. Having been able to implement only Not Chip, there is no any other gate I could use for this implementation and I have been stuck on this for days now.
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## Re: Comparison Failure for And or Or gates

 Administrator The logical behavior of a Nand gate is that of an And gate followed by a Not gate: ```A B And (Not And) 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 ```Do you see that the output of the Nand gate is always the opposite of the output of the And gate. Which means that the output of an And gate is always the opposite of the output of a Nand gate. If you have Nand and Not gates, how could you combine them to get the behavior of an And gate?
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## Re: Comparison Failure for And or Or gates

 That's exactly what I was trying to say. Based on this experience, it's clear that the combination of a Not and Nand gates cannot be used to implement an And gate. This is no longer a confusion for me as I have understood this point very clearly. However, The challenge now is, it's only the Not gate I have been able to successfully implement; which means that I cannot invoke or make reference to any of the other gates in my And gate as that will not load because one has to adhere to the bottom-up order rules of chips' implementation(e.g, Not before And, and And before Or, etc.) and the Hardware Simulator is programmed to follow these rules. So, If Nand and Not are the only two gates available to me right now, and I want to implement an And gate  that cannot be implemented with one of those gates(Nand) and I don't see the possibility of an And gate being implemented with only a Not gate. How could I possibly implement this(And) gate in this situation?
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## Re: Comparison Failure for And or Or gates

 Administrator Idrisadeniyi wrote That's exactly what I was trying to say. Based on this experience, it's clear that the combination of a Not and Nand gates cannot be used to implement an And gate. This is no longer a confusion for me as I have understood this point very clearly. No, you haven't understood the point because your understanding is currently the very opposite of the point I was trying to make. An And gate very much CAN be made using nothing but Nand and Not gates. Let's say that I have a logic function called Fred and I want to implement a new part that always outputs the opposite of whatever Fred would have output. What happens if I construct that new part by first using a Fred gate and then sending the output of that into a Not gate and using the output of the Not gate as the output of my new part?
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## Re: Comparison Failure for And or Or gates

 Thanks I really appreciate your clarification & explanation. It worked!