In your first attempt, notice that you don't use the carry signal (cary1) from the first Half Adder at all. That would only make sense if it can't have any impact on the result, but clearly it does. In the second attempt, you use the third Half Adder to add the carry signals from the other two, but then don't connect the outputs of that Half Adder to anything at all, so it might as well not be there. As a result, your overall carry signal for your Full Adder isn't connected to anything.

Personally, I think this should be treated as an error by the simulator. How it actually treats it is anyone's guess (which is why it should be treated as an error). Most logic simulators that don't treat unconnected signals as errors usually treat them as a logic LO (with no solid basis for doing so -- some real logic families, such as TTL, actually treat unconnected inputs as a logic HI, while other families, such as CMOS, can result in behavior that physically damages the chip) and I think this one is no different.

Again, go back to the math that is mapped out. Let's do it again, but this time use sn and cn as the sum and carry signals from Half Adder n.

a
b
---------
c1 s1 (HA of a+b)
c
---------
c2 s2 (HA of c+s1)
---------
c3 s3 (HA of c1+c2)

The bottom entry in each column is the final result for that bit position, so we see that our final result is a three-bit value consisting of

c3 s3 s2

But we know that the largest value we can get by adding three 1-bit values is 011, so c3 will always be a zero and is not needed.