tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:forum-32586Nabble - Hardware2024-03-28T10:58:46Z<b>Please read <a href="http://tecs-questions-and-answers-forum.52.s1.nabble.com/Hardware-Construction-Survival-Kit-tp3385741p3385741.html" target="_top" rel="nofollow" link="external">The Hardware Construction Survival Kit</a> for answers to common questions and other useful information.</b>tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037638Having problems with my ALU2024-03-15T12:15:58Z2024-03-15T12:15:58ZChance M
Hey, everyone my ALU passes all tests until it has to compute y + 1 and then the comparison fails and the output is -32750 in decimal and 1000000000010010 in binary when the output should be 0000000000010010. I can't figure out where that bit is coming from, Here's what my HDL looks like:
<br/><br/>CHIP ALU {
<br/> IN
<br/> x[16], y[16], // 16-bit inputs
<br/> zx, // zero the x input?
<br/> nx, // negate the x input?
<br/> zy, // zero the y input?
<br/> ny, // negate the y input?
<br/> f, // compute (out = x + y) or (out = x & y)?
<br/> no; // negate the out output?
<br/> OUT
<br/> out[16], // 16-bit output
<br/> zr, // if (out == 0) equals 1, else 0
<br/> ng; // if (out < 0) equals 1, else 0
<br/><br/> PARTS:
<br/> // x input
<br/> Mux16(a=x, b=false, sel=zx, out=x1);
<br/> //y input
<br/> Mux16(a=y, b=false, sel=zy, out=y1);
<br/><br/> Not16(in=x1, out=notx1);
<br/> // zx
<br/> Mux16(a=x1, b=notx1, sel=nx, out=x2);
<br/> Not16(in=y1, out=noty1);
<br/> // negate y
<br/> Mux16(a=y1, b=noty1, sel=ny, out=y2);
<br/><br/> Add16(a=x2, b=y2, out=addout);
<br/> And16(a=x2, b=y2, out=andout);
<br/> Mux16(a=andout, b=addout, sel=f, out=fout);
<br/><br/> Not16(in=fout, out=notfout);
<br/> Mux16(a=fout, b=notfout, sel=no, out=out, out[0..7]=out7, out[8..15]=out15, out[15]=isng);
<br/><br/> Or8Way(in=out7, out=zr0);
<br/> Or8Way(in=out15, out=zr1);
<br/> Or(a=zr0, b=zr1, out=zr2);
<br/> Not(in=zr2, out=zr);
<br/><br/> And(a=isng, b=true, out=ng);
<br/>
<br/>}
<br/><br/>I also have tried other people's solution and end up with the same error as well, if it matters I'm on an m1 Mac.
<p>Posted in <a href="/Chapter-2-f32594.html">Chapter 2</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037625Can't connect gate's output pin to part2024-03-13T05:27:03Z2024-03-13T05:27:03Zzicko
I have this code
<br/>/**
<br/> * FSEQ chip that performs sequential operations based on f1, f0 inputs.
<br/> * When load=0, uses output from previous step as inputs (C=Ft, D=Gt).
<br/> * When load=1, uses external inputs C and D.
<br/> */
<br/><br/>CHIP FSEQ {
<br/> IN A, B, C, D, f1, f0, Load;
<br/> OUT E, F, G;
<br/><br/> PARTS:
<br/> // Instantiate FALL chip to perform operations based on f1, f0
<br/> FALL(A=A, B=B, C=cMux, D=dMux, f1=f1, f0=f0, E=E, F=F, G=G);
<br/><br/> // Mux to select inputs c, d when load=1, or feedback from previous when load=0
<br/> Mux(a=C, b=fReg, sel=load, out=cMux);
<br/> Mux(a=D, b=gReg, sel=load, out=dMux);
<br/><br/> // Registers to store previous f, g outputs for feedback
<br/> DFF(in=F, out=fReg);
<br/> DFF(in=G, out=gReg);
<br/>}
<br/><br/>and i don't know why but its not working on line 20, it gives the error in the title. Any help would be much appreciated
<p>Posted in <a href="/Project-3-f32601.html">Project 3</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037611Output looks correct but comparison with test file fails (Not16)2024-03-01T01:53:14Z2024-03-01T01:53:14Zvbvnyk
<img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037611/2024-03-01_14-22_2.png" border="0"/><br/>// This file is part of www.nand2tetris.org
<br/>// and the book "The Elements of Computing Systems"
<br/>// by Nisan and Schocken, MIT Press.
<br/>// File name: projects/1/Not16.hdl
<br/>/**
<br/> * 16-bit Not gate:
<br/> * for i = 0, ..., 15:
<br/> * out[i] = Not(a[i])
<br/> */
<br/>CHIP Not16 {
<br/> IN in[16];
<br/> OUT out[16];
<br/><br/> PARTS:
<br/> //// Will post the code if necessary
<br/>}
<p>Posted in <a href="/Chapter-1-f32593.html">Chapter 1</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037610The currently included PC.hdl stub file has errors2024-02-26T12:54:35Z2024-02-26T12:54:35ZMBoffin
The current PC.hdl stub file in the Nand2tetris Software Suite Version 2.7 download has parentheses for the in and out bus widths, but they should be square brackets.
<br/><br/>If you don't mind me asking, what happened to these project files? It's a mess. I've run in multiple errors in the latest version of these project files. It seems like a lot of changes were made recently and then not tested at all to make sure they actually work.
<p>Posted in <a href="/Chapter-3-f32595.html">Chapter 3</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037609The currently included DMux8Way.cmp file is empty2024-02-26T11:39:02Z2024-02-26T11:39:02ZMBoffin
The current DMux8Way.cmp file in the Nand2tetris Software Suite Version 2.7 download is blank.
<br/><br/>The file should (and has in previous downloads) contain:
<br/><br/><pre>| in | sel | a | b | c | d | e | f | g | h |
| 0 | 000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 010 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 011 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 111 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 001 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 010 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 1 | 011 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 1 | 100 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 1 | 101 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 1 | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 1 | 111 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |</pre>
<p>Posted in <a href="/Chapter-1-f32593.html">Chapter 1</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037608The currently included Not16.cmp file is incorrect2024-02-26T11:06:11Z2024-02-26T11:06:11ZMBoffin
The current Not16.cmp file in the Nand2tetris Software Suite Version 2.7 download has the following contents:
<br/><br/><pre>| in | out |
| 0000000000000000 | 0000000000000000 |
| 1111111111111111 | 0000000000000000 |
| 1010101010101010 | 0000000000000000 |
| 0011110011000011 | 0000000000000000 |
| 0001001000110100 | 0000000000000000 |</pre><br/>This obviously fails whenever you try to test a working Not16.hdl file.
<br/><br/>The file should contain (and my previous downloads of the software suite contain) these contents:
<br/><br/><pre>| in | out |
| 0000000000000000 | 1111111111111111 |
| 1111111111111111 | 0000000000000000 |
| 1010101010101010 | 0101010101010101 |
| 0011110011000011 | 1100001100111100 |
| 0001001000110100 | 1110110111001011 |</pre>
<p>Posted in <a href="/Chapter-1-f32593.html">Chapter 1</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037588Hardware Simulator Error loading .hdl file2024-02-06T04:44:34Z2024-02-06T20:06:28Zsam11
I get the following error seen in the image when I try to run DMux.tst file.
<br/>Any help would be appreciated.
<br/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037588/Screenshot_2024-02-06_at_4.png" border="0" alt="Error Screenshot"/><br/><br/><a href="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037588/" target="_top" rel="nofollow" link="external">DMux.hdl file deleted</a><br/><br/><a href="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037588/DMux.tst" target="_top" rel="nofollow" link="external">DMux.tst</a>
<p>Posted in <a href="/Hardware-Simulator-f32600.html">Hardware Simulator</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037587Is nand2tetris DFF negative edge-triggered? They why is the following happening?2024-02-06T01:15:07Z2024-02-06T01:15:07Zmenkr
I have been trying to understand the behavior of the Data Flip Flop which seems to be a negative edge-triggered one, except if I change the input between the positive edge and negative edge the output is not affected.
<br/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037587/dff.gif" border="0" alt="Here's a video showing the behaviour"/>
<p>Posted in <a href="/Hardware-Simulator-f32600.html">Hardware Simulator</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4026183Hardware Simulator Won't Load Chip2013-01-28T02:01:48Z2013-02-06T15:50:41ZTim
The Hardware simulator won't load the chip below. The error is: Line 3, 'Missing CHIP' keyword.
<br/><br/>CHIP Mux4Way16 {
<br/> IN a[16], b[16], c[16], d[16], sel[2];
<br/> OUT out[16];
<br/><br/> PARTS:
<br/><i>[Functional code deleted by admin.]</i><br/>}
<p>Posted in <a href="/Hardware-Simulator-f32600.html">Hardware Simulator</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037577Coursera Unit 1.1: Boolean Function and Outcome 12024-01-20T09:27:02Z2024-01-20T09:27:02ZAzzCam
In the truth table for a Boolean function, is there a reason why we should only select the rows that result in the outcome of 1?
<p>Posted in <a href="/Chapter-1-f32593.html">Chapter 1</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037566PC logic changed?2024-01-14T09:56:14Z2024-01-14T10:39:53ZMarty Billingsley
In previous versions of Project 3, the PC logic in PC.hdl was described as:
<br/>/**
<br/> * A 16-bit counter with load and reset control bits.
<br/> * if (reset[t] == 1) out[t+1] = 0
<br/> * else if (load[t] == 1) out[t+1] = in[t]
<br/> * else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
<br/> * else out[t+1] = out[t]
<br/> */
<br/><br/>In the nand2tetris software downloaded in Jan 2024, the logic in PC.hdl is described as:
<br/>/**
<br/> * A 16-bit counter with increment, load, and reset modes.
<br/> * if (inc(t)) out(t+1) = out(t) + 1
<br/> * else if (load(t)) out(t+1) = in(t)
<br/> * else if (reset(t)) out(t+1) = 0
<br/> * else out(t+1) = out(t)
<br/> *
<br/> * To select a mode, assert the relevant control bit,
<br/> * and de-assert the other two bits.
<br/> */
<br/><br/>Obviously this changes the way the PC should be implemented. Why the change? Doesn't reset still trump everything else? It also doesn't look as if the .tst script was changed to match, which is causing my students to run into errors.
<br/><br/>Edition 2 of the book (p55) states the PC logic as the same as in edition 1 (p51).
<p>Posted in <a href="/Project-3-f32601.html">Project 3</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037562DMux error - Help needed (Fixed)2024-01-08T17:44:27Z2024-01-08T17:44:27Zjoaodjulio
// This file is part of www.nand2tetris.org
<br/>// and the book "The Elements of Computing Systems"
<br/>// by Nisan and Schocken, MIT Press.
<br/>// File name: projects/01/DMux.hdl
<br/> /**
<br/> * Demultiplexor:
<br/> * [a, b] = [in, 0] if sel == 0
<br/> * [0, in] if sel == 1
<br/> *
<br/><br/>ERROR: "Line 18, Unexpected end of file". I've been looking for a fix for this error for a long time, any help will be appreciated. Thanks in advance!
<br/><br/>EDIT: The file given is missing a "/" in the last comment. I deleted the solution, so that nobody that has the same problem can have a spoiler alert moment :)
<p>Posted in <a href="/Project-1-f32596.html">Project 1</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037517Regarding the simulator's inability to see the final test results2023-12-03T21:28:26Z2023-12-03T21:28:26ZTaussig
I can't see the horizontal bar in the bottom left corner that shows the test results when my emulator is maxed out, how can I fix this?
<br/>
<p>Posted in <a href="/Project-1-f32596.html">Project 1</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037502My submission says my ALU failed but when I test it on my side it passes?2023-12-01T15:34:55Z2023-12-01T15:37:21ZMichaelJohnOB
<a href="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037502/Screen_Shot_2023-12-01_at_5.png" target="_top" rel="nofollow" link="external">Screen_Shot_2023-12-01_at_5.png</a><br/><br/>The above is a screenshot of it passing on my side. Then when I go to submit it, I get this error:
<br/><br/><br/>Any help would be great!
<p>Posted in <a href="/Chapter-2-f32594.html">Chapter 2</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-40374731 Nand 1 = 1 ? in project 01 when buliting And gate.2023-11-03T00:26:45Z2023-11-03T00:26:45Zbanian
<img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037473/2023-11-03_152311.png" border="0"/>
<p>Posted in <a href="/Project-1-f32596.html">Project 1</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037446ALU Implementation - HELP2023-10-27T17:48:36Z2023-10-27T17:48:36Z30249
I am stuck on implementing the HDL chip. Any suggestions? Thanks.
<p>Posted in <a href="/Project-1-f32596.html">Project 1</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037450PC - Comparison failure at line 72023-10-28T22:33:23Z2023-10-28T22:33:23Zfmiren
This is my PC solution:
<br/><br/> Mux16 (a=in, b=false, sel=reset, out=outF);
<br/> Register (in=outF, load=reset, out=outRst);
<br/> Register (in=outRst, load=load, out=outLoad);
<br/> Inc16 (in=outLoad, out=outI);
<br/> Register (in=outI, load=inc, out=out);
<br/><br/>I get a comparison failure. What is my mistake? How can I fix it?
<p>Posted in <a href="/Project-3-f32601.html">Project 3</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037440How to Zoom out on hardware Simulator (page doesnt fit)2023-10-25T09:45:21Z2023-10-25T09:45:21ZFreddie2004
When loading the hardware Simulator up on my laptop, the window of the hardware simulator always occupies all up&down direction of the screen. I cannot see the report area.(highlight in red circle in below picture). it cannot be adjusted. I understand i can compare the .out file and the .cmp file by CMD. But when sth wrong with a certain line, i cannot see the error report.
<p>Posted in <a href="/Hardware-Simulator-f32600.html">Hardware Simulator</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037439RAM8 implementation2023-10-25T05:21:37Z2023-10-25T05:21:37Zfmiren
I'm struggling with RAM8 implementation. This is my code:
<br/><br/>DMux8Way (in=in, sel=address, a=outA, b=outB, c=outC, d=outD, e=outE, f=outF, g=outG, h=outH);
<br/>Mux8Way16 (a=outA, b=outB, c=outC, d=outD, e=outE, f=outF, g=outG, h=outH, sel=address, out=outmux);
<br/>Registr (in=outmux, load=load, out=out);
<br/><br/>I understand the problem with the code. In the first line, in(16) and in(1) hade different lengths. Also, outputs of DMux8Way (a, b, etc) have a length of 1, while Mux8Way16 inputs are 16-bit. I just don't know how to fix them.
<br/><br/>The main question though is whether I got logic correctly because I'm not sure I'm doing it properly. I looked at Charles Petzold's "Code" (which is a wonderful book btw) to advance my understanding of memory. Here is the circuit description from the book:
<br/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037439/Untitled.png" border="0" alt="ram8"/><br/><br/>So, I tried to implement RAM8 based on the image.
<br/><br/>Any advice/hint is appreciated.
<p>Posted in <a href="/Project-3-f32601.html">Project 3</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037376Confused about total memory allocation2023-09-23T01:30:23Z2023-09-23T01:30:23Ztxxnano
Greetings.
<br/><br/>I've encountered an architectural doubt I'd like to understand in greater depth. I managed to get in place, and this is just for the sake of complete understanding. Once resolved, I can move ahead with Chapter 5
<br/><br/>Hack computer architecture allows an addressable memory space of approximately 64KB (16-bit architecture). However, I've noticed that we've allocated only 2^15 addresses for both ROM and RAM.
<br/><br/>1. Is this allocation strategy a deliberate design choice, or is it a characteristic inherent to this specific CPU architecture where ROM and RAM maintain a 1:1 address ratio? (e.g: 2^15 for RAM + 2^15 for ROM)
<br/>2. Why the decision of a 15-bit address bus and not a 16-bit one?
<br/>3. What are the actual memory specifications of the Hack (if possible to answer)?
<br/><br/>Best regards
<br/><br/>PS: sorry for the three-question post, but I assumed they were all related.
<br/>
<p>Posted in <a href="/Chapter-3-f32595.html">Chapter 3</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037368Question about DFF chip and Clock2023-09-20T09:57:25Z2023-09-20T09:57:25ZAdam
Hello - with the DFF chip, when exactly does changing the input and the output registering it occur with regards to the clock cycle 0 0+ 1 1+ etc.
<br/><br/>For example, if the time is 0 and I set Value=1, then out will change to 1 when the time is 1.
<br/><br/>However, if the time is 0+ and I set Value=1, then out will change to 1 only when the time is 2.
<br/><br/>In other words, it seems the n+ times don't really do anything?
<br/><br/>Relating to this - how does the 0 0+ 1 1+ etc. format correspond with the 0 1 0 1 0 1 etc. format given in the book (second edition) (I assume just n is 0 and n+ is 1?), and how do these 0s and 1s correspond to a time 't' as used in the API for chips such as the DFF. I.e., we say the DFF chip has the abstraction out[t]=in[t-1], but which t is this referring to? The n or n+? Or both? And if both... how?
<br/><br/>Any help would be appreciated. Thanks!
<p>Posted in <a href="/Chapter-3-f32595.html">Chapter 3</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-27452661-bit register HDL implementation2011-03-28T14:16:22Z2011-03-28T14:16:22ZJiyda Mint Mohamed Moussa
Hello everyone,
<br/><br/>I am trying to make the 1-bit register following the figure given in the book, I understand how the register is built but my HDL implementation seems to be wrong since I get many Comparison Failures when I load the corresponding script in the Hardware simulator.
<br/>The figure is in page 43: <a href="http://www1.idc.ac.il/tecs/book/chapter%2003.pdf" target="_top" rel="nofollow" link="external">http://www1.idc.ac.il/tecs/book/chapter%2003.pdf</a><br/><br/>My HDL code:
<br/><br/>/**
<br/> * 1-bit memory register.
<br/> * If load[t-1]=1 then out[t] = in[t-1]
<br/> * else out does not change (out[t] = out[t-1])
<br/> */
<br/><br/>CHIP Bit {
<br/><br/> IN in, load;
<br/> OUT out;
<br/><br/> PARTS:
<br/> Mux(a = in, b = loopIn, sel = load, out = outMux);
<br/> DFF(in = outMux, out = loopIn, out = out);
<br/><br/><br/>}
<br/><br/>I do not see what's wrong with the code, any help is greatly appreciated!
<br/><br/><br/>
<p>Posted in <a href="/Project-3-f32601.html">Project 3</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037336How to implement RAM64KD2?2023-08-31T04:18:25Z2023-09-01T10:44:31ZXu Xian
<b>CONTENTS DELETED</b>
<div class="weak-color">The author has deleted this message.</div>
<p>Posted in <a href="/Project-3-f32601.html">Project 3</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037330How to code this design ?2023-08-23T10:25:40Z2023-09-01T10:45:37ZXu Xian
<b>CONTENTS DELETED</b>
<div class="weak-color">The author has deleted this message.</div>
<p>Posted in <a href="/Chapter-3-f32595.html">Chapter 3</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037320how to implement add32,i implemented it,but don't know what's wrong in that?2023-08-20T01:20:17Z2023-08-20T01:20:17Zpooja
is there any other way to do it?
<br/>CHIP Add32 {
<br/> IN a[32], b[32];
<br/> OUT out[32];
<br/><br/> PARTS:
<br/><br/> // First 16-bit adder
<br/> Adder16(a=a[0..15], b=b[0..15], cin=false, out=out[0..15], cout=c);
<br/><br/> // Second 16-bit adder
<br/> Adder16(a=a[16..31], b=b[16..31], cin=c, out=out[16..31], cout=c2);
<br/>}
<br/><br/>i implemented like this ,but when i'm loading the chip into the simulator
<br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037320/Screenshot_%28574%29.png" border="0"/>
<p>Posted in <a href="/Chapter-2-f32594.html">Chapter 2</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037296Mux.hdl, line 19, ',' or ')' are expected2023-07-22T01:19:15Z2023-07-22T07:52:40ZBasil Behanan
the following error shows up:
<br/>Mux.hdl, line 19, ',' or ')' are expected
<br/><br/>< CODE SNIPPED>
<br/><br/>Nand(a=not_sel,b=not_sel,out=Nand1);
<br/><br/>< CODE SNIPPED>
<br/><br/>}
<p>Posted in <a href="/Hardware-Simulator-f32600.html">Hardware Simulator</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037266The Xor demo project2023-07-06T23:57:22Z2023-07-06T23:57:22ZWBahn
In Section 1.1.4 (of the 1st Ed), the example of building an Xor gate is presented.
<br/><br/>For many people, this example causes problems because they don't realize that this example can't be implemented (in the 01 project folder) and run in the Hardware Simulator at this point and so they try to do so. The result of trying to do so is usually the following:
<br/><br/>Comparison failure at line 3
<br/><br/>Before determining what has been done wrong, let's look as exactly what this error means.
<br/><br/>When a test script is executed (and if the necessary commands are present), it produces an output file that is compared to a reference file each time that an output command is executed. If the corresponding lines in the two files do not match, an failure message is generated and the test script is aborted.
<br/><br/>After running this Xor test script, the contents of the Xor.out file is:
<br/><br/><pre>
| a | b | out |
| 0 | 0 | 0 |
| 0 | 1 | 0 |
</pre><br/>The contents of the reference file, Xor.cmp, is:
<br/><br/><pre>
| a | b | out |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
</pre><br/>As you can see, the first two lines match, but the third line does not and, hence, the comparison failure message. Note that the first line is the line with the column headers -- the comparison tool is a generic tool that is simply comparing the contents of two files.
<br/><br/>But why does the Xor.hdl part produce a 0 output when 'a' is a 0 and 'b' is a 1? The logic in the file would certainly indicate that the output should be a 1.
<br/><br/>The problem isn't in the Xor.hdl file at all. The problem is that the Xor.hdl file uses several parts, namely the Not, the Or, and the And, that have not yet been implemented. But the skeleton files for them DO exist in the 01 folder, and so the simulator does find implementations for them, but those implementations do not contain any logic.
<br/><br/>Ideally, the simulator would produce some kind of error message when a design uses an output from a part that is not defined. Unfortunately, this simulator generally behaves as if that signal has a 0 value.
<br/><br/>There are two ways to deal with this. The first is to define the parts that are used and the second is to force the simulator to use its built-in versions of those parts. The first option doesn't apply in this case, since the whole point of the example is to see how the Xor gate can be implemented before starting the Chapter 01 project. To use the second option, we leverage the fact that when the simulator sees a reference to a part, such as the Not gate in the first line of the Xor logic design, it first looks for an HDL file with that name in the same directory. If it finds it, it loads it; but if it fails to find that file, it uses the built-in model for that part instead.
<br/><br/>So one way to get our Xor.hdl to work before implementing the other parts is to delete, move, or rename the HDL files for the Not, the And, and the Or gates.
<br/><br/>While this will work, the authors have provided a folder named 'demo' that contains all of the files needed to execute the Xor gate using the built-in chips. This folder isn't mentioned in the test because it was added after the book was published in response to this common stumbling block.
<br/><br/>
<p>Posted in <a href="/Chapter-1-f32593.html">Chapter 1</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037234Comparison Failure for "AND" gate2023-06-24T09:04:11Z2023-06-24T09:04:11Zmohamad.ismail
<img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037234/Screen_Shot1_2023-06-24_at_12.png" border="0"/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037234/Screen_Shot2_2023-06-24_at_12.png" border="0"/><br/><br/><br/>Please help. what am i missing here? why is there a comparison failure?
<br/><br/>Also, which line is line 5 exactly?
<p>Posted in <a href="/Chapter-1-f32593.html">Chapter 1</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037221Ram82023-06-19T10:20:49Z2023-06-22T11:50:07Zron2308
Hi, I would be grateful for you help. I thought I have figured out the right code, but it is not the case. Internal pins are created but not the required outcome.
<br/><br/>My code is a follows:
<br/> <code snipped><br/> Mux8Way16(a=out1,b=out2,c=out3,d=out4,e=out5,f=out6,g=out7,h=out8,sel=address,out=out);
<br/>
<br/>Please help me to figure out what is wrong.
<br/>Sincerely, Ron
<p>Posted in <a href="/Chapter-3-f32595.html">Chapter 3</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4025885OSX "Permission Denied": HardwareSimulator.sh2012-12-18T22:22:12Z2012-12-18T22:22:12ZConnor
According to Finder, HardwareSimulator.sh is located in: /Users/connor/Desktop/nand2tetris/tools
<br/><br/>So, in my terminal I entered: /Users/connor/Desktop/nand2tetris/tools/HardwareSimulator.sh &
<br/><br/>The terminal returns:
<br/><br/>[2] 5000
<br/>Connor:tools connor$ -bash: /Users/connor/Desktop/nand2tetris/tools/HardwareSimulator.sh: Permission denied
<br/><br/>[2]+ Exit 126 /Users/connor/Desktop/nand2tetris/tools/HardwareSimulator.sh
<br/><br/>... and then no program runs
<br/><br/>I'm no mac whiz, so thanks in advance if there is a very obvious fix :)
<p>Posted in <a href="/Hardware-Simulator-f32600.html">Hardware Simulator</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037147need help understanding binary numbers w.r.t the hack ALU ng out.2023-04-27T02:29:53Z2023-04-27T03:10:28Zstranger
i'm a bit confused,and would like to understand something,the most-significant-bit(MSB),the first bit/sign bit in a 2s complement number of e.g a 16 bit output "out[16]" would be listed as the "out[15]"? i was confused when "out[0]" didn't work for the control logic of the ng output bit for the Hack ALU,and searched for help and "out[15]" worked,i was confused because i thought the first bit aka "out[0]" would act as the sign bit/MSB
<p>Posted in <a href="/Chapter-2-f32594.html">Chapter 2</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037140Hardware simulator acting strange, or am I the problem?2023-04-26T15:19:20Z2023-04-26T15:47:10Zligman stichdeez
I'm implementing the mux4way16, where I chose to build a Mux4way chip first, then use it in the Mux4way16. When I load mux4way.hdl, it doesn't work. However, when I load/test mux4way16.hdl, it works perfectly. What could be the issue?
<br/><br/>Edit: I figured it out.. Chips have to have the same name as the file in which they are located
<br/>Mux4Way.hdl:
<br/>CHIP Mux4Way{
<br/> .....
<br/>}
<p>Posted in <a href="/Hardware-Simulator-f32600.html">Hardware Simulator</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037134testing multiple bit gates (values interpretation)2023-04-26T02:03:53Z2023-04-26T02:03:53Zlodowcowy_rowerzysta
Can someone explain me how to interpret values of pins that are shown in hardware simulator while testing gates with multiple bit input? For example:
<br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037134/Zrzut_ekranu_2023-04-26_105206.jpg" border="0"/><br/>why input 0001 0010 0011 0100 corresponds with value 4660, input 1001 1000 0111 0110 corresponds with value -26506 and value of output is 4148? I am also curious what "%B" means in the script.
<p>Posted in <a href="/Hardware-Simulator-f32600.html">Hardware Simulator</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-40371312 bit multiplier?2023-04-24T21:31:08Z2023-04-25T07:16:32ZMrPostnikov
I am not sure if anyone every tired this, but after solving for the ALU part, wanted to add more to the chip.
<br/>I wanted to add a multiplication capabilities.
<br/><br/>This is the implement I tired:
<br/><br/> CHIP Mul2bit {
<br/> IN a[2], b[2];
<br/> OUT out[4];
<br/><br/> PARTS:
<br/> // First row of AND gates
<br/> And(a=a[0], b=b[0], out=c0);
<br/> And(a=a[0], b=b[1], out=w1);
<br/><br/> // Second row of AND gates
<br/> And(a=a[1], b=b[0], out=w2);
<br/> And(a=a[1], b=b[1], out=w3);
<br/><br/> // First half adder
<br/> HalfAdder(a=w1, b=w2, sum=c1, carry=carry1);
<br/><br/> // Second half adder
<br/> HalfAdder(a=w3, b=carry1, sum=c2, carry=c3);
<br/><br/>}
<br/><br/>I also tried this as well:
<br/><br/>CHIP Mul2bit{
<br/> IN a[2], b[2];
<br/> OUT out;
<br/><br/> PARTS:
<br/>
<br/> And(a=a[0], b=b[1], out=w1);
<br/> And(a=a[0], b=b[0], out=c0);
<br/>
<br/> And(a=a[1], b=b[0], out=w2);
<br/> And(a=a[1], b=b[1], out=w3);
<br/> And(a=w1, b=w2, out=w4);
<br/> And(a=w4, b=w3, out=c3);
<br/>
<br/>
<br/> Xor(a=w1, b=w2, out=c1);
<br/> Xor(a=w4, b=w3, out=c2);
<br/>}
<br/><br/>However, the problem I was having is that I needed to make a .tst and the .cmp files. I don't understand the .cmp, I am not sure what exactly it does. I also don't quite understand how the .tst file should be written with what syntax. Has anyone tired to make a custom chip? If you did make a custom chip did you have to write your own .tst file and .cmp file?
<br/><br/>Some other questions I have is that, I was planning on building it up to 4bit multiplier, that said, would I need to implement it into the ALU and all of its .tst file and .cmp? Meaning would I need to update the truth table in .cmp file?
<br/><br/>NOTE I CHANGED THE QUESTIONS A BIT TO MAKE IT MORE CLEAR WHAT I AM ASKING!
<br/>
<p>Posted in <a href="/Chapter-2-f32594.html">Chapter 2</a></p>
tag:nand2tetris-questions-and-answers-forum.52.s1.nabble.com,2006:post-4037127stuck Loading chip...2023-04-22T06:04:58Z2023-04-22T06:04:58ZSnape
I meet a problem
<br/>when i use Hardware simulator to load Mux.hdl and any mux-related files.
<br/>The simulator always present " Loading chip". And stay in this state. 【picture1】
<br/>But when i load other chip which can be loaded normally. 【picture2】
<br/><br/>However, if I load the original unedited chip, it loads fine.【picture3】
<br/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037127/error.png" border="0"/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037127/other.png" border="0"/><br/><img src="http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/file/n4037127/nothing.png" border="0"/>
<p>Posted in <a href="/Chapter-1-f32593.html">Chapter 1</a></p>