

At first I thought this exercise would be easy because Full Adder truth table clearly tells that when a is 0 the sum will be a XOR, the carry will be an AND; when a is 1 the sum will be an inverted XOR, the carry will be an inverted AND. I've used what I learned in chapter 1 to synthesize a function from the truth table and I've also done the kmap but I can't for the life of me "translate" none of that to HDL: I'm trying to use Half Adders but it only accepts 2 variables, which means that it will generate only 4 outputs rather than the 8 outputs needed. Even if for a miracle I got 2 HAs to generate the correct outputs I have no clue how to tie them together in order to have the whole sum and carry with 8 outputs each.
I've rewatched the videos, reread the chapter and I guess I'm not even close to understand, I'm feeling so dumb. This is the first time we deal with 3 variables and 2 outputs in the course, isn't it? It would really help if someone could tell me what happens step by step, I'm not used to this 3 inputs/2 outputs configuration at all.

Administrator

penpaperglass wrote
At first I thought this exercise would be easy because Full Adder truth table clearly tells that when a is 0 the sum will be a XOR, the carry will be an AND; when a is 1 the sum will be an inverted XOR, the carry will be an inverted AND.
Take a look again very carefully at that last claim (that the carry, when a=1, is an inverted AND).
I've used what I learned in chapter 1 to synthesize a function from the truth table and I've also done the kmap but I can't for the life of me "translate" none of that to HDL: I'm trying to use Half Adders but it only accepts 2 variables, which means that it will generate only 4 outputs rather than the 8 outputs needed. Even if for a miracle I got 2 HAs to generate the correct outputs I have no clue how to tie them together in order to have the whole sum and carry with 8 outputs each.
What 8 outputs. A Full Adder has 3 inputs and 2 outputs. Not 8.
I've rewatched the videos, reread the chapter and I guess I'm not even close to understand, I'm feeling so dumb. This is the first time we deal with 3 variables and 2 outputs in the course, isn't it? It would really help if someone could tell me what happens step by step, I'm not used to this 3 inputs/2 outputs configuration at all.
In Chapter 1 the DMux4Way had three inputs and four outputs while the DMux8Way had four inputs and eight outputs.
What if someone just asked you do design a chip, call it FA_sum, that took the three inputs (a,b,c) and produced a single output that was just the sum output. Could you make that chip?
What if someone just asked you do design a chip, call it FA_carry, that took the three inputs (a,b,c) and produced a single output that was just the carry output. Could you make that chip?
If someone gave you the FA_sum and FA_carry chips, could you use those to make an FullAdder chip?


WBahn wrote
Take a look again very carefully at that last claim (that the carry, when a=1, is an inverted AND).
You're right, thank you. Inverted AND is completely wrong.
What 8 outputs. A Full Adder has 3 inputs and 2 outputs. Not 8.
What I meant is that when you give 2 inputs to a Half Adder it will not generate the 8 different combinations of zeros and ones to the sum and carry, only 4. Like this:
a  b  sum  carry
0  0  0  0
0  1  1  0
1  0  1  0
1  1  0  1
Rather than this:
a  b  sum  carry
0  0  0  0
0  0  0  0
0  1  1  0
0  1  1  0
1  0  1  0
1  0  1  0
1  1  0  1
1  1  0  1
What if someone just asked you do design a chip, call it FA_sum, that took the three inputs (a,b,c) and produced a single output that was just the sum output. Could you make that chip?
What if someone just asked you do design a chip, call it FA_carry, that took the three inputs (a,b,c) and produced a single output that was just the carry output. Could you make that chip?
If someone gave you the FA_sum and FA_carry chips, could you use those to make an FullAdder chip?
I guess I would fall into the same problem I'm here asking for help.
What happens is that I'm limited by the way I think how the Half Adder works. It seems impossible to me to use any of the OUT (sum, carry) because, as I typed in the 2nd quote in this post, HA can only generate 4 different combinations of zeros and ones, not 8 and even if I could get both halves of the Full Adder right using 2 HAs I wouldn't know how to combine those halves to get the Full Adder working.
I hope that you understood what I meant now. Thanks for helping.

Administrator

Forget about the Half Adder completely. If it's leading you into a blind alley, don't even start there.
If I give you a truth table that has three inputs, x, y, and z, and a single output, out, you should be able to come up with a digital logic circuit that implements that truth table. If you can't, then you need to pause and get to the point where you can do that. Otherwise you are just digging yourself a deeper hole with each step you take.
So what would you do if I asked you to design a circuit that matches a truth table in which the output is always 0 except when the xinput is 0, the yinput is 1, and the zinput is 1? Can you come with with a logic circuit that does that?


WBahn wrote
Forget about the Half Adder completely. If it's leading you into a blind alley, don't even start there.
If I give you a truth table that has three inputs, x, y, and z, and a single output, out, you should be able to come up with a digital logic circuit that implements that truth table. If you can't, then you need to pause and get to the point where you can do that. Otherwise you are just digging yourself a deeper hole with each step you take.
So what would you do if I asked you to design a circuit that matches a truth table in which the output is always 0 except when the xinput is 0, the yinput is 1, and the zinput is 1? Can you come with with a logic circuit that does that?
For some reason I've put in my mind that the Half Adder would stop executing once the input a reached its last 0 in the truth table, that's why I couldn't understand what happened and I kept telling you about "4 combinations of zeros and ones in the outputs, not 8". I'd say a strong fear of being wrong may have caused myself to lock my mind to believe that nonsense.
Now that I've come back to my normal self I solved the Full Adder using 2 Half Adders and one Or, finally!
if I asked you to design a circuit that matches a truth table in which the output is always 0 except when the xinput is 0, the yinput is 1, and the zinput is 1? Can you come with with a logic circuit that does that?
This would be my answer, is it correct?
Not(in=x, out=notX);
And(a=notX, b=y, out=notXAndY);
And(a=notXAndY, b=z, out=out);
WBahn, I really appreciate your help and patience. Thank you a lot! Also I'm really sorry for this nonsense I've come up with, I feel so dumb and stupid.

Administrator

penpaperglass wrote
if I asked you to design a circuit that matches a truth table in which the output is always 0 except when the xinput is 0, the yinput is 1, and the zinput is 1? Can you come with with a logic circuit that does that?
This would be my answer, is it correct?
Not(in=x, out=notX);
And(a=notX, b=y, out=notXAndY);
And(a=notXAndY, b=z, out=out);
That's correct. I think you've got it since you got the FA down.
WBahn, I really appreciate your help and patience. Thank you a lot! Also I'm really sorry for this nonsense I've come up with, I feel so dumb and stupid.
Not a problem at all  we all brainlock from time to time.

