# Is someone able to see my misstake?

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## Is someone able to see my misstake?

 This post was updated on . I should represent that with the simulator. For this I have created myself xor, xnor, not and and. Therefore it is not the built-in "xor", "xnor", "not" and "and". However, they work just as well as the built-in. But I have an error, although I do not see it, because I think I created the code correctly, does anyone see it? CHIP test{ //b0=in[2], b1=in[4], b2=in[5], b3=in[6] //s1=in[0], s2=in[1], s3=in[3]         IN in[7];         OUT out[4];                 PARTS:                 //R1         Xor(a=in[2], b=in[4], out=a);         Xor(a=a, b=in[6], out=b);                 //R2         Xor(a=in[2],b=in[5],out=c);         Xor(a=c, b=in[6], out=d);                 //R3         Xor(a=in[4],b=in[6],out=e);         Xor(a=e,b=in[5],out=f);                 //C1         Xnor(a=b,b=in[0], out=h);         //C2         Xnor(a=d,b=in[1], out=j);         //C3         Xnor(a=f,b=in[3], out=l);                         Not(in=h1, out=hh);         Not(in=j1, out=jj);         Not(in=l1, out=ll);                 //cb0         And(a=hh, b=jj, out=m);         And(a=m, b=l, out=n);                 //cb1         And(a=hh, b=j, out=o);         And(a=o, b=ll, out=p);                 //cb2         And(a=h, b=jj, out=q);         And(a=q, b=l, out=r);                 //cb3         And(a=hh, b=jj, out=s);         And(a=s, b=ll, out=t);                 //b0         Xor(a=in[2], b=n, out=out[0]);         //b1         Xor(a=in[4], b=p, out=out[1]);         //b2         Xor(a=in[5], b=r, out=out[2]);         //b3         Xor(a=in[6], b=t, out=out[3]);                                 }
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## Re: Is someone able to see my misstake?

 Administrator What part is this supposed to be? Your HDL says that this chip is called "test".