It seems like the chips I wrote in Chapter 1 and 2 aren't actually being used.

[song]

For example, when creating the Mux in Chapter 1, I used the And chip, but it looks like it's not using the one I implemented, and instead it's using a built-in version.

I'm about to start Chapter 2, but it feels like the files I wrote in Chapter 1 aren't being used.
If all the tests have passed, then I guess it's not a big issue—but still, I wish the files I wrote were actually being used.

[Renslay]

In the same chapter the software should use your chip implementations. If you made the And chip, the Mux chip should use that implementation. Make sure the syntax is correct (e.g., you made an "And" chip and not an "and" chip).

However, later chapters won't use the chips of the previous chapters. Chapter 2 won't use your Mux chips. The reason is simple: performance. It's always faster to use the built-in chips (the reason lies in how the emulator works).

If your chips pass the tests, you learned the lesson anyway. Each chapter is another abstraction layer, where you can ignore / forget how the previous layer was actually implemented.

By the way, I recreated the various chips in a logic circuit simulator. My first approach was exactly this: the high level chips used my implementation of the low level chips, which used the even lower level chips, and so on. It was painfully slow by the end, practically unusable. It was much better once I used the built-in chips (there were all kind of chips, from Nand and Mux to Ram/Rom chips).

[WBahn]

song wrote

For example, when creating the Mux in Chapter 1, I used the And chip, but it looks like it's not using the one I implemented, and instead it's using a built-in version.

I'm about to start Chapter 2, but it feels like the files I wrote in Chapter 1 aren't being used.
If all the tests have passed, then I guess it's not a big issue—but still, I wish the files I wrote were actually being used.

That is correct. The authors very intentionally made it so that each chapter's projects were independent of the other chapters, as much as possible. This allows students to do them in almost any order. If you want to skip the combinatorial logic and jump straight into sequential logic, the you can just start with Chapter 3. Similarly, if you want to focus on the top-level architecture without dealing with the weeds, just start with Chapter 5 (or perhaps Chapter 4).

If you WANT to force the simulator to use your implementations from prior chapters, just copy over the HDL files from those chapters into the current chapter -- but be prepared for a huge performance penalty in the simulator.

This is also why Chapter 3 is partitioned into two parts, because simulating the larger memory chips all the way down to the DFF level makes them glacially slow in the simulator.