I have implemented the RAM in the way that I think is suggested by the conferences and the chips previously developed. Essentially:
- DMux the load flag.
- Probe each inferior level RAM or register / read and, if required, rewrite the addressed register.
- Mux the output.
But this implementation seems to me very inefficient, because for each read or write operation, we need to probe all the registers in the RAM (16K). That seems to be because Mux and DMux operate with contents, not with instructions, so we can not just route an instruction to read or write to a specified register. Is this so or am I missing something?
Even if it has to be like that in the Hack computer, I presume it is not like that in real computers. Am I right? How can this be achieved?
How are we probing all of the registers in the RAM?
We are using the contents of the A register to set the control bits on several Mux and Demux parts. There is a chain of such parts in series, but in worst case there are only as many as there are bits in the address. But it isn't anywhere near that bad because we can use decoders and encoders to work with multiple bits at once. The optimal layout depends on a number of factors, many of which depend on the technology being used to implement the hardware, but others depend on the higher-level architectural decisions such as whether the design is pipelined.
Maybe I´m missing something, but this is the way I see it:
- In teh RAM16K chip we invoke four RAM4k chips.
- In each RAM4K chip we invoke eight Ram512 chips
- And so on down to the RAM8 chip.
- In the RAM8 chip we invoke eight register chips.
- In the register chip we read the register and pull it out
- We select one of these outputs with the DMux command in the RAM8 chip.
- In the RAM 64 chip we pull each of the RAM8 outputs and Dmux them.
- And so on back to the RAM16K chip.
So we are probing all the registers just to read one, aren´t we?
Not at all -- probing implies we are going from register to register and checking its value. All of the Registers in RAM are always providing their outputs to the inputs of the Muxes they are directly connected to. Three of the address bits in the A register route 1/8 of these values up to the next layer of Muxes, where some more of the address bits prune the selection further. In theory, we could have a 16k-to-1 Mux that takes a 15-bit input and directly selects one of the registers to present to the output. In practice, it would be unusual to do this. Usually address decoders seldom work with more than five to seven bits directly for a variety of hardware implementation issues. But four and to six bits is pretty common. That's for static RAM. I'm not too familiar with the internals of DRAM chips and they would have a potentially different set of limitations (and opportunities) to work with.