Will the HACK CPU know how to stall when loading from memory if implemented on real hardware or FPGA? Or is that an implementation detail that was trimmed off of the CPU for the purposes of the course?
The need for stalls is driven by one part of the design running faster than another part can handle. The easiest solution is to run the machine at a speed dictated by the slowest part (the critical path). Lots of systems do just this, particularly cheap, resource-starved, embedded systems. But to get better performance, most systems choose to run the main part of the system as fast as it can and then compensate for the slower parts as needed. Hence stall states.
If you were to build the Hack in hardware, the most sensible thing to do would be to run it no faster than the critical speed and call it a day.