Can't really help massively at the moment, but what my help you (and I do this regularly before starting a project) is go through all the previous posts on chapter 5 or posts on the PC (the search bar isn't too bad on Nabble). There's several years worth, you might find some of your questions already answered. There's been a lot of questions recently about that topic too. I'd be very surprised if you didn't pick up some good hints...
Sorry am unable to help you more than that atm (it's 1.30 am where I'm at and i've still got some chores to do and I need help with chapter 9! )
I'll no doubt be on in a couple of days time hoping someone's answered my question so maybe I can be more helpful then..
I find that it really helps to draw the schematic of what the HDL represented, but that may be more reflective of my particular background than anything else.
Ask yourself under what circumstances the value stored in the Register should change. Your current design only changes this value when the 'load' signal is asserted. But what if just the 'reset' signal is asserted? Is it enough to just have the output for the current clock cycle be low? What about the next clock cycle? Consider the following:
Let's say that t = 513 and we have the following:
out[t=513] = 10000
in[t=513] = 12345
reset[t=513] = 1
inc[t=513] = 0
load[t=513] = 0
The specs say:
* A 16-bit counter with load and reset control bits.
* if (reset[t] == 1) out[t+1] = 0
* else if (load[t] == 1) out[t+1] = in[t]
* else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
* else out[t+1] = out[t]
So out[t=514] should be 0. Your circuit actually makes the output at t=513 equal to 0 because the effect of your control signals on the Muxes routes the False (0) to the output immediately upon the control signals changing.
But aside from that (i.e., let's assume that your circuit made out[t=514] equal to zero like it should), what about the next clock cycle if
In this case the output at t=515 should be 1, but your circuit still has 10000 stored in the Register, so your output will go to 10001, which is definitely not what you want.
For any situation in which the new output is related to the prior output, your circuit must store that prior output so that it can use it during the next clock cycle. So what you are really controlling is the value to be stored in the register on each clock cycle. Look at the problem from that perspective.
The order of statements in the HDL has no effect at all. All they do is describe which pin on one part is connected to which wire.
The reason that your two versions don't behave the same has nothing to do with statement ordering. It's because the two versions are for two very different circuits. Map them out and you will see what I mean.
Or just walk through a couple of situations with each. For instance, what happens if all three control signals are HI (a 1)?