# Why does my zr implementation give me the error: can't connect gate's output pin to part?

 Classic List Threaded
3 messages
Reply | Threaded
Open this post in threaded view
|

## Why does my zr implementation give me the error: can't connect gate's output pin to part?

 Implementation:    Or8Way(in=out[0..7], out=aa);    Or8Way(in=out[8..15], out=bb);    Or(a=aa, b=bb, out=zr);
Reply | Threaded
Open this post in threaded view
|

## Re: Why does my zr implementation give me the error: can't connect gate's output pin to part?

 Nvm, I fixed it: Spoiler for the working ALU design - // This file is part of www.nand2tetris.org // and the book "The Elements of Computing Systems" // by Nisan and Schocken, MIT Press. // File name: projects/02/ALU.hdl /**  * The ALU (Arithmetic Logic Unit).  * Computes one of the following functions:  * x+y, x-y, y-x, 0, 1, -1, x, y, -x, -y, !x, !y,  * x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs,  * according to 6 input bits denoted zx,nx,zy,ny,f,no.  * In addition, the ALU computes two 1-bit outputs:  * if the ALU output == 0, zr is set to 1; otherwise zr is set to 0;  * if the ALU output < 0, ng is set to 1; otherwise ng is set to 0.  */ // Implementation: the ALU logic manipulates the x and y inputs // and operates on the resulting values, as follows: // if (zx == 1) set x = 0        // 16-bit constant // if (nx == 1) set x = !x       // bitwise not // if (zy == 1) set y = 0        // 16-bit constant // if (ny == 1) set y = !y       // bitwise not // if (f == 1)  set out = x + y  // integer 2's complement addition // if (f == 0)  set out = x & y  // bitwise and // if (no == 1) set out = !out   // bitwise not // if (out == 0) set zr = 1 // if (out < 0) set ng = 1 CHIP ALU {     IN           x[16], y[16],  // 16-bit inputs                 zx, // zero the x input?         nx, // negate the x input?         zy, // zero the y input?         ny, // negate the y input?         f,  // compute out = x + y (if 1) or x & y (if 0)         no; // negate the out output?     OUT         out[16], // 16-bit output         zr, // 1 if (out == 0), 0 otherwise         ng; // 1 if (out < 0),  0 otherwise     PARTS:    // Put you code here:    //Implement zx    Mux16(a=x, b=false, sel=zx, out=zxx);        //Implement zy    Mux16(a=y, b=false, sel=zy, out=zyy);    //Implement nx    Not16(in = zxx, out = notzxx);    Mux16(a = zxx, b = notzxx, sel = nx, out = zxnxx);    //Implement ny    Not16(in = zyy, out = notzyy);    Mux16(a = zyy, b = notzyy, sel = ny, out = zynyy);    //Implement f    And16(a= zxnxx, b= zynyy, out= andxy);    Add16(a= zxnxx, b= zynyy, out= addxy);    Mux16(a= andxy, b=addxy, sel=f, out= fout);    //Inverse if no and also ng    Not16(in=fout, out=nfout);    Mux16(a=fout, b=nfout, sel=no, out = out, out=finalout, out[15] = ng, out[0..7] = firsthalf,out[8..15] = secondhalf );    //zr    Or8Way(in=firsthalf, out=a);    Or8Way(in=secondhalf, out=b);    Or(a=a, b=b, out=notzr);        Not(in = notzr, out = zr); }
Reply | Threaded
Open this post in threaded view
|

## Re: Why does my zr implementation give me the error: can't connect gate's output pin to part?

 Administrator In reply to this post by Password Please remove you ALU solution code. As you discovered, the key to the issue (and something that is admittedly not well documented) lies in the error message that says that the problem is that you can't connect the gate's output pin to a part. It might be a bit more obvious if the message said "chip's output pin" instead of "gate's output pin", but maybe not. In your original implementation, you are using the chip's 'out' output as in input to two Or8Way gates. This HDL does not allow that (I'm guessing it made the simulator's implementation easier to put on that restriction, I've never seen another HDL that imposed that constraint). Furthermore, in another unusual constraint, you can't tap subbusses off of internal signals the way that you tried. The solution is to provide additional internal signals separate from the output signals and perform the subbussing with the part's output pins, as you did with your 'firsthalf' and 'secondhalf' signals. It looks like you still have a legacy signal from trying to solve this problem in that you have a copy of the output (your 'finalout' signal) that is never actually used. The two HDL constraints and the rather kludgy way that you have to circumvent them is unfortunate. It has been a stumbling block for many, many people -- which in and of itself detracts from the learning and enjoyment of the course -- and it makes for code that is much more obtuse and hard to follow than it could be.