# error message "A pin name is expected" when testing the ALU

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## error message "A pin name is expected" when testing the ALU

 I've built my ALU, but whenever I try to load it into the Hardware Simulator I get the error message: "In HDL file C:\nand2tetris\nand2tetris\projects\02\ALU.hdl, line 51, a pin name is expected." line 51 is the first component of my ALU, a Mux:     Mux(a=x[0], b=zero, sel=zx, out=1x0); To my understanding, the error message implies that this line is missing some component pin, but i can't figure out where I went wrong.  The only thing I can think of is the b=zero component, since I did not define what "zero" is, but that should default the value to 0 (since it's an unconnected input pin).  Ive also tried explicitly defining "zero" by adding this Xor:     Xor(a=x[0], b=x[0], out=zero); but this changed nothing. Here's my full ALU: // This file is part of www.nand2tetris.org // and the book "The Elements of Computing Systems" // by Nisan and Schocken, MIT Press. // File name: projects/02/ALU.hdl /**  * The ALU. Computes one of the following functions:  * x+y, x-y, y–x, 0, 1, -1, x, y, -x, -y, !x, !y,  * x+1, y+1, x-1, y-1, x&y, x|y on two 16-bit inputs.  * Which function to compute is determined by 6 input bits  * denoted zx, nx, zy, ny, f, no.  * The computed function's value is called "out".  * In addition to computing out, the ALU computes two  * 1-bit outputs called zr and ng:  * if out == 0, zr = 1; otherwise zr = 0;  * If out < 0, ng = 1; otherwise ng = 0.  * The 6-bit combinations (zx,nx,zy,ny,f,no) and  * their effect are documented in the book.  */ // Implementation: the ALU manipulates the x and y // inputs and then operates on the resulting values, // as follows: // if (zx  == 1) sets x = 0        // 16-bit constant // if (nx  == 1) sets x = ~x       // bitwise "not" // if (zy  == 1) sets y = 0        // 16-bit constant // if (ny  == 1) sets y = ~y       // bitwise "not" // if (f   == 1) sets out = x + y  // integer 2's-complement addition // if (f   == 0) sets out = x & y  // bitwise And // if (no  == 1) sets out = ~out   // bitwise Not // if (out == 0) sets zr = 1 // if (out < 0)  sets ng = 1   CHIP ALU {     IN           x[16], y[16],  // 16-bit inputs                 zx, // zero the x input?         nx, // negate the x input?         zy, // zero the y input?         ny, // negate the y input?         f,  // compute  out = x + y (if f == 1) or out = x & y (if == 0)         no; // negate the out output?     OUT         out[16], // 16-bit output         zr, // 1 if (out == 0), 0 otherwise         ng; // 1 if (out < 0),  0 otherwise     PARTS:     Mux(a=x[0], b=zero, sel=zx, out=1x0);     Mux(a=x[1], b=zero, sel=zx, out=1x1);     Mux(a=x[2], b=zero, sel=zx, out=1x2);     Mux(a=x[3], b=zero, sel=zx, out=1x3);     Mux(a=x[4], b=zero, sel=zx, out=1x4);     Mux(a=x[5], b=zero, sel=zx, out=1x5);     Mux(a=x[6], b=zero, sel=zx, out=1x6);     Mux(a=x[7], b=zero, sel=zx, out=1x7);     Mux(a=x[8], b=zero, sel=zx, out=1x8);     Mux(a=x[9], b=zero, sel=zx, out=1x9);     Mux(a=x[10], b=zero, sel=zx, out=1x10);     Mux(a=x[11], b=zero, sel=zx, out=1x11);     Mux(a=x[12], b=zero, sel=zx, out=1x12);     Mux(a=x[13], b=zero, sel=zx, out=1x13);     Mux(a=x[14], b=zero, sel=zx, out=1x14);     Mux(a=x[15], b=zero, sel=zx, out=1x15);     Xor(a=1x0, b=nx, out=2x0);     Xor(a=1x1, b=nx, out=2x1);     Xor(a=1x2, b=nx, out=2x2);     Xor(a=1x3, b=nx, out=2x3);     Xor(a=1x4, b=nx, out=2x4);     Xor(a=1x5, b=nx, out=2x5);     Xor(a=1x6, b=nx, out=2x6);     Xor(a=1x7, b=nx, out=2x7);     Xor(a=1x8, b=nx, out=2x8);     Xor(a=1x9, b=nx, out=2x9);     Xor(a=1x10, b=nx, out=2x10);     Xor(a=1x11, b=nx, out=2x11);     Xor(a=1x12, b=nx, out=2x12);     Xor(a=1x13, b=nx, out=2x13);     Xor(a=1x14, b=nx, out=2x14);     Xor(a=1x15, b=nx, out=2x15);     Mux(a=y[0], b=zero, sel=zy, out=1y0);     Mux(a=y[1], b=zero, sel=zy, out=1y1);     Mux(a=y[2], b=zero, sel=zy, out=1y2);     Mux(a=y[3], b=zero, sel=zy, out=1y3);     Mux(a=y[4], b=zero, sel=zy, out=1y4);     Mux(a=y[5], b=zero, sel=zy, out=1y5);     Mux(a=y[6], b=zero, sel=zy, out=1y6);     Mux(a=y[7], b=zero, sel=zy, out=1y7);     Mux(a=y[8], b=zero, sel=zy, out=1y8);     Mux(a=y[9], b=zero, sel=zy, out=1y9);     Mux(a=y[10], b=zero, sel=zy, out=1y10);     Mux(a=y[11], b=zero, sel=zy, out=1y11);     Mux(a=y[12], b=zero, sel=zy, out=1y12);     Mux(a=y[13], b=zero, sel=zy, out=1y13);     Mux(a=y[14], b=zero, sel=zy, out=1y14);     Mux(a=y[15], b=zero, sel=zy, out=1y15);     Xor(a=1y0, b=ny, out=2y0);     Xor(a=1y1, b=ny, out=2y1);     Xor(a=1y2, b=ny, out=2y2);     Xor(a=1y3, b=ny, out=2y3);     Xor(a=1y4, b=ny, out=2y4);     Xor(a=1y5, b=ny, out=2y5);     Xor(a=1y6, b=ny, out=2y6);     Xor(a=1y7, b=ny, out=2y7);     Xor(a=1y8, b=ny, out=2y8);     Xor(a=1y9, b=ny, out=2y9);     Xor(a=1y10, b=ny, out=2y10);     Xor(a=1y11, b=ny, out=2y11);     Xor(a=1y12, b=ny, out=2y12);     Xor(a=1y13, b=ny, out=2y13);     Xor(a=1y14, b=ny, out=2y14);     Xor(a=1y15, b=ny, out=2y15);     HalfAdd(a=2x0, b=2y0, sum=sum0, carry=carry1);     FullAdd(a=2x1, b=2y1, c=carry1, sum=sum1, carry=carry2);     FullAdd(a=2x2, b=2y2, c=carry2, sum=sum2, carry=carry3);     FullAdd(a=2x3, b=2y3, c=carry3, sum=sum3, carry=carry4);     FullAdd(a=2x4, b=2y4, c=carry4, sum=sum4, carry=carry5);     FullAdd(a=2x5, b=2y5, c=carry5, sum=sum5, carry=carry6);     FullAdd(a=2x6, b=2y6, c=carry6, sum=sum6, carry=carry7);     FullAdd(a=2x7, b=2y7, c=carry7, sum=sum7, carry=carry8);     FullAdd(a=2x8, b=2y8, c=carry8, sum=sum8, carry=carry9);     FullAdd(a=2x9, b=2y9, c=carry9, sum=sum9, carry=carry10);     FullAdd(a=2x10, b=2y10, c=carry10, sum=sum10, carry=carry11);     FullAdd(a=2x11, b=2y11, c=carry11, sum=sum11, carry=carry12);     FullAdd(a=2x12, b=2y12, c=carry12, sum=sum12, carry=carry13);     FullAdd(a=2x13, b=2y13, c=carry13, sum=sum13, carry=carry14);     FullAdd(a=2x14, b=2y14, c=carry14, sum=sum14, carry=carry15);     FullAdd(a=2x15, b=2y15, c=carry15, sum=sum15, carry=carry16);     And(a=2x0, b=2y0, out=and0);     And(a=2x1, b=2y1, out=and1);     And(a=2x2, b=2y2, out=and2);     And(a=2x3, b=2y3, out=and3);     And(a=2x4, b=2y4, out=and4);     And(a=2x5, b=2y5, out=and5);     And(a=2x6, b=2y6, out=and6);     And(a=2x7, b=2y7, out=and7);     And(a=2x8, b=2y8, out=and8);     And(a=2x9, b=2y9, out=and9);     And(a=2x10, b=2y10, out=and10);     And(a=2x11, b=2y11, out=and11);     And(a=2x12, b=2y12, out=and12);     And(a=2x13, b=2y13, out=and13);     And(a=2x14, b=2y14, out=and14);     And(a=2x15, b=2y15, out=and15);     Dmux(a=and0, b=sum0, sel=f, out=almost0);     Dmux(a=and1, b=sum1, sel=f, out=almost1);     Dmux(a=and2, b=sum2, sel=f, out=almost2);     Dmux(a=and3, b=sum3, sel=f, out=almost3);     Dmux(a=and4, b=sum4, sel=f, out=almost4);     Dmux(a=and5, b=sum5, sel=f, out=almost5);     Dmux(a=and6, b=sum6, sel=f, out=almost6);     Dmux(a=and7, b=sum7, sel=f, out=almost7);     Dmux(a=and8, b=sum8, sel=f, out=almost8);     Dmux(a=and9, b=sum9, sel=f, out=almost9);     Dmux(a=and10, b=sum10, sel=f, out=almost10);     Dmux(a=and11, b=sum11, sel=f, out=almost11);     Dmux(a=and12, b=sum12, sel=f, out=almost12);     Dmux(a=and13, b=sum13, sel=f, out=almost13);     Dmux(a=and14, b=sum14, sel=f, out=almost14);     Dmux(a=and15, b=sum15, sel=f, out=almost15);     Not(in=almost0, out=notout0);     Not(in=almost1, out=notout1);     Not(in=almost2, out=notout2);     Not(in=almost3, out=notout3);     Not(in=almost4, out=notout4);     Not(in=almost5, out=notout5);     Not(in=almost6, out=notout6);     Not(in=almost7, out=notout7);     Not(in=almost8, out=notout8);     Not(in=almost9, out=notout9);     Not(in=almost10, out=notout10);     Not(in=almost11, out=notout11);     Not(in=almost12, out=notout12);     Not(in=almost13, out=notout13);     Not(in=almost14, out=notout14);     Not(in=almost15, out=notout15);     Dmux(a=almost0, b=notout0, sel=no, out=out[0]);     Dmux(a=almost1, b=notout1, sel=no, out=out[1]);     Dmux(a=almost2, b=notout2, sel=no, out=out[2]);     Dmux(a=almost3, b=notout3, sel=no, out=out[3]);     Dmux(a=almost4, b=notout4, sel=no, out=out[4]);     Dmux(a=almost5, b=notout5, sel=no, out=out[5]);     Dmux(a=almost6, b=notout6, sel=no, out=out[6]);     Dmux(a=almost7, b=notout7, sel=no, out=out[7]);     Dmux(a=almost8, b=notout8, sel=no, out=out[8]);     Dmux(a=almost9, b=notout9, sel=no, out=out[9]);     Dmux(a=almost10, b=notout10, sel=no, out=out[10]);     Dmux(a=almost11, b=notout11, sel=no, out=out[11]);     Dmux(a=almost12, b=notout12, sel=no, out=out[12]);     Dmux(a=almost13, b=notout13, sel=no, out=out[13]);     Dmux(a=almost14, b=notout14, sel=no, out=out[14]);     Dmux(a=almost15, b=notout15, sel=no, out=out[15]);     Or(a=out[0], b=out[1], out=1nzr);     Or(a=1nzr, b=out[2], out=2nzr);     Or(a=2nzr, b=out[3], out=3nzr);     Or(a=3nzr, b=out[4], out=4nzr);     Or(a=4nzr, b=out[5], out=5nzr);     Or(a=5nzr, b=out[6], out=6nzr);     Or(a=6nzr, b=out[7], out=7nzr);     Or(a=7nzr, b=out[8], out=8nzr);     Or(a=8nzr, b=out[9], out=9nzr);     Or(a=9nzr, b=out[10], out=10nzr);     Or(a=10nzr, b=out[11], out=11nzr);     Or(a=11nzr, b=out[12], out=12nzr);     Or(a=12nzr, b=out[13], out=13nzr);     Or(a=13nzr, b=out[14], out=14nzr);     Or(a=14nzr, b=out[15], out=ng);     Not(in=ng, out=zr); }
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## Re: error message "A pin name is expected" when testing the ALU

 Administrator You want to use the built-in constant "false". This is an extremely hard way to write the ALU. There is a reason why you have been building 16-bit wide chips. --Mark
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## Re: error message "A pin name is expected" when testing the ALU

 Changing "zero" to "false" doesn't change the error message that I get. I realize now how to do the ALU more easily with the 16-bit chips, but I wasn't sure of how to do the syntax correctly at first so I built it all out of 1-bit chips.  I could probably do it over with 16-bit chips, but I wanted to see if this implementation worked first (which is where I ran into the error message).