Since this is my first post in this forum I would like to begin by thanking some of you for the time you put into answering questions on this forum. They have helped me out on several occasions and are invaluable.
I have just completed my implementation of the PC and I have a question about a (minor?) detail of my implementation.
In the last step of the PC we have to update/read the register. If reset, load and inc are all 0, we could basically output the current state of the register. But since the logic doesn't really change the out(t-1) in this case, we could just always set the load to 1 in the register, and set the in to the current internal out. This would write to the register every clock cycle of the PC.
Register(in=rnew, load=true, out=new, out=out);
My question is whether this is bad practice. It's easily fixable by doing a double OR on the input flags of the PC.
Or(a=reset, b=load, out=l1);
Or(a=l1, b=inc, out=l2);
Register(in=rnew, load=l2, out=new, out=out);
Note that both these cases work fine, and result in the PC HDL implementation passing the tests, but I wonder if the second case would result in a more performant PC.