Okay, that gives me some context to make a (hopefully) more meaningful explanation.
Connections in this (and many) HDLs are made not by position, but by name. So, for instance, you can take the Nand gate and write it as
Nand(a=tom, b = sue, out=fred);
and this is completely identical to
Nand(b = sue, out = fred, a=tom);
For parts with a bus connection, think of the bus pins as collections of multiple separate pins (which is exactly what they are).
So, for instance, the Or8Way(in, out) doesn't have two parameters, it has nine separate, distinct connections. For our convenience (and sanity), they allow us to connect multiple pins at a time, provided they are adjacent in the bus. So we can have something like:
Or8Way(in = sue, out = fred, in[0..2] = tom, out = karen, in[4..7] = bob);
provided sue is a single bit signal, tom is a 3-bit signal, and bob is a 4-bit signal).
Notice that out is used twice. This is fine. In fact, this is the only way to connect the output of a gate to other gates as well as an output of the overall chip. Think of the signals as physical wires and all we are doing is connecting the wire named 'fred' to the output of the Or8Way chip as well as connecting the signal named 'karen' to it.
What is important (and not always enforced by the tools, which leads to very hard to diagnose runtime problems) is that every input signal must be connected to exactly one driving signal -- either an input of the overall chip or an output of some other part within the design.
Outputs do not have to be connected to anything. Of course, if the part only has a single output, then there's no value in using the part if the output isn't connected. But some parts have multiple outputs and if we don't need to use them all, then we can ignore the ones we don't need and just use the ones we do.