2's Compliment Representation of Signed Numbers

[ismithers]

So just thinking about chapter 2 after completing it the other night. I wanted to double-check I understand this sort of representation. Does it mean that with the 16bit ALU, our maximum numbers are 15 bit in size, due to the final bit being used for signing?

Also out of interest, later on is multiplication and division added to this ALU, or is that beyond the scope of the book?

Thanks!
Ian

[cadet1620]

ismithers wrote

So just thinking about chapter 2 after completing it the other night. I wanted to double-check I understand this sort of representation. Does it mean that with the 16bit ALU, our maximum numbers are 15 bit in size, due to the final bit being used for signing?

Also out of interest, later on is multiplication and division added to this ALU, or is that beyond the scope of the book?

Thanks!
Ian

That's correct. 16-bit two's complement numbers have maximum values that are +/- 15 bits. The exact range is from -32768 to 32767.

Multiplication and division hardware is not developed in the Nand2Tetris course. Software implementation of multiplication and division is done when writing the OS in chapter 12.

--Mark

[ismithers]

Is implementing * and / on a logic gate scale quite a lot of work compared to addition of signed integers? Also I've noticed that as I look at the forum there are less and less posts in each subsequent chapter forum - is this because people know what they are doing by that stage or have they given up and gone away as it gets much tougher? I'm dying to get to the machine language section! :)

[cadet1620]

ismithers wrote

Is implementing * and / on a logic gate scale quite a lot of work compared to addition of signed integers? Also I've noticed that as I look at the forum there are less and less posts in each subsequent chapter forum - is this because people know what they are doing by that stage or have they given up and gone away as it gets much tougher? I'm dying to get to the machine language section! :)

The simplest hardware multiplier implements the long multiplication algorithm that we leaned in primary school, but in binary rather than decimal.  For instance multiplying 11 * 13 = 143:

    1011
    1101
    ----
    1011
   0000
  1011
 1011
--------
10001111

The partial products are generated by Anding each bit of the multiplicand with each bit of the multiplier. The partial products are then summed using adders. A 16-bit multiplier will need 256 And gates to generate the partial products and 15 16-bit adders to sum them!

As to the drop out rate...

I think that the forum is mostly used by independent students. Many of them only do the hardware portion of the course because that's the part of the book that's available on line for free.

I've also seen several students who are already experienced programmers who did the hardware part of the course because they wanted to learn how their computers really worked at the low level. Those who also do the software portion don't ask many questions except for the VM Translator chapters.

Independent students with minimal programming experience often have a tough time with the VM Translator and stop there. I sometimes end up working with them via off-forum email. It seems about half of them are persistent enough to get through it.

--Mark

[ismithers]

I sort of wish I had more time as I would love to write that and then implement some tests to see if it worked. But at the moment I'm just going to crack on. I can always come back later should I wish to. Makes you appreciate how insanely complex our CPUs of today must be, despite being built with very simple blocks of logic!