A little BIT problem

[utsav]

In a BIT gate, one input for Mux is the output of DFF and input of DFF is output of Mux at previous time unit . I understand how it works from second clock cycle , but for the very first cycle(I mean, just when the circuit is switched on),there is no output from Mux at previous time unit. So what is the input for Mux at very first clock cycle.

[cadet1620]

At time t=0 the output of the DFF is defined to be 0, so if load is 0 the output of the Mux will be 0. The Bit will be reliably initialized to 0.

In the real world, on power up the state of a DFF will be either 0 or 1 so the bit will be either 0 or 1. Care must be taken that the overall circuit gets set to a known state by a power on reset signal.

--Mark

[utsav]

Okay, for HW simulator it can be done but in the real world how can the DFF be either 0 or 1 on power up ?

[cadet1620]

Play-hookey is a good site to learn how DFFs are built from elementary gates. Start with the RS Nand Latch.

The basic storage element in sequential logic is cross coupled Nand (or Nor) gates:
        
This circuit is stable in either state when the /Set and /Reset inputs are high. The simplest explanation for why one state or the other will occur at power up is that /Set or /Reset will go true before the other since there is no such thing as simultaneous in the real world.

In the real world, power doesn't come up instantaneously either. It can take several milliseconds for the power supply to provide stable, full voltage, power. This is where the dirty secret of digital hardware is exposed: there is really no such thing as digital hardware. All digital hardware is actually very high gain analog circuits. At that level, IC designers need to be analog engineers and ensure that their circuits behave sanely under the abnormal conditions during power up.

--Mark