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 Hi. Ive been able to create a w lenght of 16 bits by 8 registers. It is pretty cool. I am thinking that if I had another chip it will each register at choice be selected. It does not seem to emit the values when I select a register and load. I am confused why. Can you explain how the ram knows a particular number it stores. I included a picture. Hopefully this is the correst design.
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 Now I am really confused. I created a chip that goes from 16 bits left to right and then 8 registers going up to down. Just like the picture shows in the book. Then I connected them to a dmux8way to be able to select them at "random" with three selects. The api of the hardware simpulator requires three imputs? The chip has one imput for a value to go in at selcted register. How is that wrong? I guess where I was really even more confused was how it needed to take in a 16 bit value. Im aware that this one created can only take in a 1 bit value. Can you explain some more? The only way that I could think that a switch to be able to select a register is the way I did.
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 Administrator This post was updated on . So I'm assuming that you have a total of 128 1-bit registers organized as 8 rows with 16 registers in each row. Okay, let's work with that. You data input is not one bit, but sixteen bits. Your three address lines select which row you want those sixteen bits to go into. The other rows are left unchanged. The only row that gets changed is the one row that corresponds to the 3-bit value on the address signal lines. This is done by using those three lines to assert the 'load' signal to every register on the corresponding line, but the 'load' signal to every register on all of the other seven rows has to be kept LO (a 0). Each column is one bit in the 16-bit input/output word. You can order them any way you want. If it's easiest to think of the leftmost column being the most-significant bit and the rightmost column being the least-significant bit, that's fine. Let's go with that for now. The most-significant bit of the input is set to the data input of all eight registers in the leftmost column. But since the load will only be asserted for one of the rows, seven of them will be unaffected and the msb of the input value will be stored in the leftmost register of the chosen row. The same happens for each of the other fifteen bits in the input value using the other fifteen columns.