ABOUT REGISTERS

[Dan1984mor2017]

Hi. I have a problem. I am attempting to create a register. I think I have it figured out, but I am unsure. The question I have is this: Is a register a sequence of bits from left to right. I am confused because in the requirements on the book it says 16 input and 16 outputs. The only way that I can think to create that is by making a chip with the bits going virtical from up to down leaving the circuits open as I think. But if I string it from left to right I will only be left with one input and one ouput? Can you help?

[WBahn]

Each bit in a multibit register is independent other than having a common write signal.

Think of a 16-bit register as being a place to store sixteen pieces of information. One of those bits might be whether it is day or night and other might be whether the door is open or closed. These are unrelated and so the notion of left-to-right or top-to-bottom has no meaning. If you assign bit #5 to hold the information about whether it is day or night, then all you care about is that when you write a value to bit #5 at the input, that if you later read bit #5 at the output that you get the same value you previously wrote.

The only thing the bits have in common is that if you write to one of the bits you must write to all of them at the same time.

[Dan1984mor2017]

I understand what you are saying in regards to memory size and actuality of using it, but I am confused what the book on page 49 is requiring.

[WBahn]

What, specifically, is it on page 49 that you are referring to?

There is nothing there that talks about up/down or left/right.

A part, in this case a Register, is a black box. Inside of that black box are other parts that are connected together in some way so as to implement the interface specification given.

In this case this black box has 17 inputs. One of them is called 'load' and the other sixteen are named in[0] through in[15], which can be referred to collectively as just 'in', which represents all of these inputs as a group. There are 16 outputs, named out[0] through out[15], which again can be referred to collectively as just 'out'.

Think of the specification for a 'bit'. Doesn't it look just like the specification for one of the sixteen in[?] and out[?] pairs in a Register?

What if all you did was connect a single 'bit' part within the Register black box such that the 'bit' part's 'in' port was connected to to in[3], the 'out' port was connected to out[3], and the 'load' port was connected to 'load'? Would you not get the exact behavior you want for a 16-bit Register, at least as far as that one signal is concerned? How could you then get similar behavior for the other fifteen signals?