ALU - Don't know where to start

[Technik]

I've been staring blankly at page 37 for a couple of days now trying to figure out what step to take next in building the ALU. I seem to be stuck.

I saw a Logisim schematic posted in a thread around here and was trying to follow along, but I feel like that's cheating myself out of figuring it out.

Any tips? I've completed all the prior chips for this and the last chapter.

[cadet1620]

Look at the text in Figure 2.5. There function description is lots of "ifs". The easiest way to make choices in hardware is with Multiplexors -- generate both signals you might need and select the one you do need.

Be sure to read Appendix A.5.3; you'll want to use sub-busing to make the status bits. Also read how "true" and "false" constants work.

This post has test files that only test the arithmetic part of the ALU which makes it easier to build.  Once the arithmetic works you can concentrate on the status flags.

--Mark

[Technik]

Ah! Thanks for the help. I'm a little confused about these status bits. What exactly are ng and zr and what purpose do they serve? The rest make sense (zx = zero X; ny = negate y, etc) but I'm not sure I understand what the "status" bits are.

[cadet1620]

Technik wrote

What exactly are ng and zr and what purpose do they serve? The rest make sense (zx = zero X; ny = negate y, etc) but I'm not sure I understand what the "status" bits are.

The status bits give information about the numerical value of the ALU's output. If the output is 0, then zr is true. If the output is a negative number, then ng is true. If the output is a positive number, both status bits are false.

The status bits will be used in project 5 to implement conditional jumps in the CPU.

--Mark

[Technik]

Hey,

Had to take a break for a while, but I'm back again. I've drawn out and coded what I think is a pretty good description of the math circuit (haven't got to the status bits).

When I try to test, it says comparison failure at line 3. Here's my output:

|        x         |        y         |zx |nx |zy |ny | f |no |       out        |
| 0000000000000000 | 1111111111111111 | 1 | 0 | 1 | 0 | 1 | 0 | 0000000000000000 |
| 0000000000000000 | 1111111111111111 | 1 | 1 | 1 | 1 | 1 | 1 | 1111111111111111 |

Which according to the alu-nostat.cmp file, should be fifteen 0s and a 1 at the end instead of sixteen 1s. Not sure I understand what's going on with that.

Mind if I PM you a picture of my sketch & the HDL I've written thus far?

[cadet1620]

Technik wrote

Mind if I PM you a picture of my sketch & the HDL I've written thus far?

Please do send your sketch and HDL. I'll be happy to look at it.

--Mark

[Technik]

Thanks! Just sent you an e-mail :)

[Technik]

Still trying to work out the status bits. I think I might have the right idea for zr, but I'm not sure. When I write it up in HDL, the simulator says "Can't connect gate's output pin to part" but I'm not sure where else I can pull from.

I am trying to split 'out' into 8 wires and feed it into 2 Or8Way modules. I looked at A.5.3 but I still don't understand.

[cadet1620]

You can have more than one "out=" connection on a part.

On the part that generates the ALU out, add more out connections that generate the sub-buses you need to connect to the Or8Ways.

--Mark

[Technik]

Woohoo! Comparison ended successfully!

Thanks for your help, Mark!