Building a new type of CPU chip, can't understand the pin change

[Liur1996]

I'm working on a new type of CPU chip for an assignment, the difference is that the D register is replace by a bank of 4 register and the input to that bank is controlled by 2 read access outa[2] and outb[2], 1 write access inc[2]. on top of that their is an added Jump instruction. I have modified the code to suit the new changes but the problem is that every time after the new input line shows up the register banks load pin would change after the register has been loaded, but the input line does not have a bit that set register load to 1, but it would stay on 1 from the previous line and change after the data in A register is sent to register bank.

    Mux16(a=ALUOut, b=instruction, sel=Noper, out=Muxout);    
    Not(in=instruction[15],out=Noper);
    And(a=instruction[0],b=instruction[2],out=destA);
    Or(a=Noper, b=destA, out=loadA);
    ARegister(in=Muxout, load=loadA, out[0..14]=addressM, out=RegA);    
       
    Not(in=instruction[2],out=Dbar);
    And(a=instruction[15],b=instruction[14],out=Dinst);           CHANGES HERE
    And(a=Dbar,b=Dinst,out=loadD);
RegisterBank4(in=ALUOut,load=loadD,ina=instruction[5..6],inb=instruction[3..4],inc=instruction[0..1],outa=Da,outb=Db);                                                                           CHANGES HERE IN inc

    Mux4Way16(a=false,b=Db,c=RegA,d=inM, sel=instruction[12..13], out=DbAM);
    ALU(x=Da, y=DbAM, zx=instruction[11], nx=instruction[10], zy=false, ny=instruction[8], f=instruction[7], no=instruction[6], out=outM, out=ALUOut, zr=O, ng=lt);
    And(a=instruction[2],b=instruction[1],out=toM);
    And(a=toM, b=instruction[14], out=writeM);          

    Or(a=O, b=lt, out=lte);                                              
    Not(in=lte, out=pos);
    And(a=instruction[2], b=lt, out=jlt);                                
    And(a=instruction[1], b=O, out=jeq);
    And(a=instruction[0], b=pos, out=jgt);
    Or(a=jlt, b=jeq, out=tempj);                                        
    Or(a=tempj, b=jgt, out=jumpor);
    Not(in=instruction[14],out=J);
    And(a=instruction[15],b=J,out=Jjump);
    And(a=Jjump, b=jumpor, out=jump);
    PC(in=RegA, load=jump, inc=true, reset=reset, out[0..14]=pc, out[15]=abc);

Since I can't attach files, I can't show the new line structure and related information, but if anyone has a vague idea of the error, any help is appreciated

[cadet1620]

It will be a while before I can take a look at your HDL. What's the encoding for the new instructions?

You're the second poster today about this project; I'm curious what course this is for.

--Mark

[cadet1620]

Liur1996 wrote

every time after the new input line shows up the register banks load pin would change after the register has been loaded, but the input line does not have a bit that set register load to 1, but it would stay on 1 from the previous line and change after the data in A register is sent to register bank.

Are you talking about the values shown in the compare/output at time Tn and time Tn+? If so, you may be have been misled by the built-in D- and ARegister displaying their value changing at time Tn+. The D- and ARegister outputs do not change at Tn+1. What is being shown is their 'in' value at that time.

You should look at the output from CPU-external.tst and compare that timing to your new CPU's timing.

Two things that I see in your HDL:

instruction[6] conflict?
    RegisterBank4(... ina=instruction[5..6]
    ALU(... no=instruction[6]
I suspect ny, f, no s/b inst[9, 8, 7]

writeM decoding appears to be incorrect; think about @ instructions.

--Mark

[Liur1996]

I will try my best to write the new encoding
A instruction are as normal 0xxxxxxxxxxxxxxx
D instruction are 11s1s2 c1c2c4c5c6 a1a2 b1b2 d1d2d3
11 indicates this is an D instruction s1s2 refers to operand 2, c1-6 is for the ALU, a1a2 is operand 1 and is for selecting 1 of the 4 register in registerbank do A read access, b1b2 is no an operand but is for selecting 1 of the register to do B read access, d1-d3 is the destination bits
d1 d2 d3              a1/b1   a2/b2           s1    s2
0   0   0     D_0     0         0      D_0      0     0      0
0   0   1     D_1     0         1      D_1      0     1      d_b
0   1   0     D_2     1         0      D_2      1     0      A
0   1   1     D_3     1         1      D_3      1     1      AM
1   0   0     null
1   0   1     A
1   1   0     M
1   1   1     AM
The J instruction is the same as D instruction but starts with 10 and d1-d3 changes j1-j3
j1  j2  j3
0   0   0 null
0   0   1 JGT
0   1   0 JEQ
0   1   1 JGE
1   0   0 JLT
1   0   1 JNE
1   1   0 JLE
1   1   1 JMP
The major difference between this structure and the diagram on the chapter 5 note is that D register is replace with 4 data register bank, and the Mux before the ALU changes to a 4 way Mux where 00=false, 01=d_b,10=A,11=M, also the data register bank also output an d_a straight to the ALU, but you probably notice that from the code.

This is a assignment for a uni course, the course corriculum had a change so the lecturer decides to make the new 4D bit as a continued assignment from project 05, I couldn't get much help from the lecturer so all I can do is seek help somewhere else.

[cadet1620]

Sent reply by email.

Still asleep today, forgot to fill in the subject line.  Check your spam trap!

--Mark