Bus cycle of a hack machine (state diagram)

[bourhano]

Hello, I've been reading this book and I noticed that the Fetch/Execute cycle is 'almost'-never broke down to pieces.

In order to create a state diagram of a microprocessor you need to know exactly the external inputs that affect the Fetch/Execute cycle. In our case, I can't think of none but the reset signal that is able to break the cycle.

But is it synchronous or asynchronous? does it wait till the whole instruction is executed to reset or it happens directly upon arrival? or are there other signals that affect the cycle?
Knowing this piece of information is what let me create the bus cycle of the machine.
Thanks for contributing!

[WBahn]

The fine details are unspecified because they are dictated by the CPU Emulator (and other tools as appropriate) in such a way that you have little, if any, control over them.

But part of your question is specified -- the reset signal affects that Hack by being a signal into the PC component and it's behavior is specified to the same degree for the 'reset' input as it is for any of the other inputs. The output of the PC (which is the ROM address) changes ONLY with the clock.