horhen wrote
im not quite getting what to do.
The supplied "task" in the CPU.hdl seems to be puzzling to me. I don't understand how the inputs of the CPU.hdl affects its output. I would appreciate it if someone could give me a mathematical explanation of the task. By "mathematical" I meant in equation form. e.g. if reset == 1 then out(t) = in(t-1)... thanks.
The CPU implementation is described in 5.3.1 and accompanied by an block diagram in figure 5.9. Everything in the diagram, except "decode," is one of the parts that you have built or a supplied part (ARegister and DRegister). The circled C signals are the "control signals" that are connected to the part inputs that are not explicitly shown in the diagram.
For instance, the PC needs to have signals for its
load and
inc. It's the job of "decode" to generate these signals based on bits in
instruction and the ALU's
zr and
ng.
Starting with figure 5.9 you can develop your own detailed specification. It might look something like:
AinMux.a = ALU.out
AinMux.b = instruction
AinMux.sel = Decode.ain_select
Areg.in = AinMux.out
Areg.load = Decode.areg_load
The main challenge is to determine the required logic for the control signals. Think about how the various instructions you used writing the Project 4 programs work.
--Mark
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