Because the Hack CPU executes every instruction in one clock cycle, there is no pipelining to be done.
Pipelining basically allows instructions that take more than one clock cycle to overlap. A simple example would be if all instructions took 3 clock cycles: fetch, decode and execute. The cycles must execute one after another
| t0 | t1 | t2 | t3 | t4 | t5 |
| fetch1 | decode1 | execute1 | fetch2 | decode2 | execute2 |
With pipelining, the CPU has independent hardware for each instruction phase, so the phases can overlap
| t0 | t1 | t2 | t3 | t4 | t5 |
| fetch1 | decode1 | execute1 |
| fetch2 | decode2 | execute2 |
| fetch3 | decode3 | execute3 |
| fetch4 | decode4 | execute4 |
There are many complications to pipelining. The simplest is when the pipeline is broken due to a jump. For instance, say instruction2 in the above example is a jump to instruction 8
| t0 | t1 | t2 | t3 | t4 | t5 | t6 | t7 |
| fetch1 | decode1 | execute1 |
| fetch2 | decode2 | execute2 |
| fetch3 | decode3 | *
| fetch4 | *
| fetch8 | decode8 | execute8 |
| fetch9 | decode9 | execute9 |
* Notice that instruction3 and instruction4 must be abandoned when they have been partially executed.
Pipelining gets very complex when you are dealing with a processor that has variable length instructions and variable cycle counts for different instructions.
(Issues related to abandoning partially executed instructions are what are being exploited in the Meltdown and Spectre hacks.)
--Mark
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