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I have this code
/**
* FSEQ chip that performs sequential operations based on f1, f0 inputs.
* When load=0, uses output from previous step as inputs (C=Ft, D=Gt).
* When load=1, uses external inputs C and D.
*/
CHIP FSEQ {
IN A, B, C, D, f1, f0, Load;
OUT E, F, G;
PARTS:
// Instantiate FALL chip to perform operations based on f1, f0
FALL(A=A, B=B, C=cMux, D=dMux, f1=f1, f0=f0, E=E, F=F, G=G);
// Mux to select inputs c, d when load=1, or feedback from previous when load=0
Mux(a=C, b=fReg, sel=load, out=cMux);
Mux(a=D, b=gReg, sel=load, out=dMux);
// Registers to store previous f, g outputs for feedback
DFF(in=F, out=fReg);
DFF(in=G, out=gReg);
}
and i don't know why but its not working on line 20, it gives the error in the title. Any help would be much appreciated
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Administrator
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It's a bit hard to tell because I don't know which pins on your gates are inputs and which one are outputs.
If line 20 is the one with the FALL part and if E, F, and G are output pins, then connecting those to the output of the chip shouldn't be a problem.
But in the two DFF gates that you have at the bottom, you are applying a chip output to a gate input, and this HDL doesn't support that. But there's a way around that.
Let's say that you have a Not gate whose output is needed both for the chip output and as an input to another gate within the part. You simply use the gate output twice.
Not(in=a, out=chipOut, out=internalOut);
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for the FALL chip, a, b, c, d, f1, f0 are all inputs and e, f, g are outputs. So you're telling me i should do this instead, DFF(in=F, out=fReg, out=freg2) for example? or am I missing something?
one more thing, i wanted to check if this circuit will do what its suppose to do in the comment, will it?
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Administrator
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You've got the problem backwards.
Your chip has E, F, and G defined as outputs.
That means that E, F, and G signals can only be tied to the output of a part.
Your DFF part has them tied to the input of the DFF, and that is not allowed.
So whatever part is producing the F output, have it produce a copy of that output and use that copy as the input to other parts where needed.
As for whether your logic is correct, which signal do you want to appear at the output of the Mux if Load is 1? Which signal will appear at the output of the Mux if Load is 1?
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I made the copies, it worked, thank you so much
when Load = 1 will enable you to load new inputs to Ct and Dt and when set to 0 sets Ct+1 = Ft and Dt+1 = Gt. The Load input will allow you to manually set the values of C and D at the start and during the sequence if required.
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Administrator
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It sounds like what you WANT to have happen is that, when Load = 1, that the inputs from the C and D outputs will appear at the output of the two Muxes. Is that correct?
If that is correct, take a step back and forget about what you want to have happen, and look at the circuit with the goal of determining what WILL happen.
When Load = 1, which signal is presented to the output of the Muxes? Is it the signal connected to the 'a' input, or the signal connected to the 'b' input?
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when load=1, c/d should be presented and it should be signaled to 'b' right?
whats the next step?
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Administrator
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zicko wrote
when load=1, c/d should be presented and it should be signaled to 'b' right?
whats the next step?
Yes. C and D should go to the 'b' input.
But what input are they actually going to in your circuit?
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Locked
