Can't connect output pin to part...?

[eVh1955]

Hardware Simulator refuses to open it, saying that the output pin at line 42 cannot be connected to part?  

That should be the first line Mux16.  Its out is supposed to be connected to the A register.  All are supposed to be 16 bits but why would they not connect?  Thanks.

PARTS:
Mux16(a=instruction, b=outM, sel=instruction[15], out=forAreg);  
ARegister(in=forAreg, load=outM[5], out=addressM);
PC(in[15]=instruction[15],in[0..14]=addressM, load=,inc=,reset=reset,out[0..14]=pc,out[15]=discard);
Mux16(a=addressM,b=inM,sel=c,out=MuxToALU);  ALU(x=DToALU,y=MuxToALU,zx=instruction[11],nx=instruction[10],zy=instruction[9],ny=instruction[8],f=instruction[7],no=instruction[6],out=outM, out[3]=writeM, zr=zeroOrNot, ng=lessZeroOrNot);
DRegister(in=outM, load=outM[4], out=DToALU);

[WBahn]

Attach the actual file. Often times the problem is earlier in the file.

Also, describe exactly how you are trying to open it. There are several ways that the simulator can open a file.

[eVh1955]

CPU.hdl

I just open the hardware simulator and try to open the file there.  That message will pop out.



// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/05/CPU.hdl

/**
 * The Hack CPU (Central Processing unit), consisting of an ALU,
 * two registers named A and D, and a program counter named PC.
 * The CPU is designed to fetch and execute instructions written in
 * the Hack machine language. In particular, functions as follows:
 * Executes the inputted instruction according to the Hack machine
 * language specification. The D and A in the language specification
 * refer to CPU-resident registers, while M refers to the external
 * memory location addressed by A, i.e. to Memory[A]. The inM input
 * holds the value of this location. If the current instruction needs
 * to write a value to M, the value is placed in outM, the address
 * of the target location is placed in the addressM output, and the
 * writeM control bit is asserted. (When writeM==0, any value may
 * appear in outM). The outM and writeM outputs are combinational:
 * they are affected instantaneously by the execution of the current
 * instruction. The addressM and pc outputs are clocked: although they
 * are affected by the execution of the current instruction, they commit
 * to their new values only in the next time step. If reset==1 then the
 * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
 * than to the address resulting from executing the current instruction.
 */

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M?
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    Mux16(a=instruction, b=outM, sel=instruction[15], out=forAreg);  
    ARegister(in=forAreg, load=outM[5], out=addressM);
    PC(in[15]=instruction[15],in[0..14]=addressM, load=,inc=,reset=reset,out[0..14]=pc,out[15]=discard);
    Mux16(a=addressM,b=inM,sel=c,out=MuxToALU);
    ALU(x=DToALU,y=MuxToALU,zx=instruction[11],nx=instruction[10],zy=instruction[9],ny=instruction[8],f=instruction[7],no=instruction[6],out=outM, out[3]=writeM, zr=zeroOrNot, ng=lessZeroOrNot);
    DRegister(in=outM, load=outM[4], out=DToALU);


   


   
}

[WBahn]

Look at the line it is complaining about carefully:

Mux16(a=instruction, b=outM, sel=instruction[15], out=forAreg);  

Of those four pins on the Mux16, which are inputs and which are outputs of that part?

An output of a part can only be connected to inputs of other parts or outputs of the overall chip.

In input of a part can only be connected to the output of another part of the input of the overall chip.

[eVh1955]

For that Mux16 line there is only one out, and that is out=forAreg.  And that is supposed to be connected to the input of A-register.  I understand that forAreg is 16 bits and the input of A-register accepts 16 bits.  Yet it was still rejected.  What else did I miss?  

[WBahn]

eVh1955 wrote

For that Mux16 line there is only one out, and that is out=forAreg.  And that is supposed to be connected to the input of A-register.  I understand that forAreg is 16 bits and the input of A-register accepts 16 bits.  Yet it was still rejected.  What else did I miss?

Yes. There is only one output for the Mux16. But I asked specifically about ALL the pins, both input and output. Don't just focus on one pin.

Think carefully about what I said about the inputs to parts. They can be connected to the outputs of other parts or to the inputs of the overall chip.

They can't be connected to the outputs of the overall chip.

[eVh1955]

Hi.  I resolved the problem...a little bit.  

But now the error is: Line 44 missing '.'

What is the problem this time?

CPU.hdl

Line 44 is at the ARegister.  Thanks.

    PARTS:
    Mux16(a=instruction, b=instruction, sel=instruction[15], out=firstOut);
    Mux(a=instruction[15],b=instruction[5], sel=instruction[15], out=loadForA)  
    ARegister(in=firstOut, load=loadForA, out=addressM);  
    PC(in[15]=instruction[15],in[0..14]=addressM, load=,inc=true,reset=reset,out[0..14]=pc);
    Mux16(a=addressM,b=inM,sel=instruction[12],out=MuxToALU);
    ALU(x=DToALU,y=MuxToALU,zx=instruction[11],nx=instruction[10],zy=instruction[9],ny=instruction[8],f=instruction[7],no=instruction[6],out=outM, out[3]=writeM, zr=zeroOrNot, ng=lessZeroOrNot);
    DRegister(in=outM, load=outM[4], out=DToALU);

[WBahn]

In general, if you don't see anything on the line it reports, look at the line immediately before it.

[eVh1955]

The errors have stopped. Test still return errors though.  But that is for another thread.  Thank you.