Can you help me to figure why this chip is not working?

[GustavoB]

CONTENTS DELETED

The author has deleted this message.

[cadet1620]

GustavoB wrote

I've made the OR chip, look:

CHIP OR {
IN a,b;
OUT out;
PARTS:
NOT(in=a,out=a1);
...

But it's not working. I'm trying to run the comparison script and it gives me a comparison failure at line 3. I've built the same chip on Logisim and it works. What am I doing wrong?

There is likely to be some problem with your NOT.hdl.

You should be naming your parts and files exactly as they are in the book including character case. Windows in particular can get confused by case differences.  When you get to more complex parts in chapter 3, you must use the built-in parts because there is not enough memory for the simulator to handle the circuit complexity.  There are hundreds of thousands of Nand gates in the larger RAMs.

[Please edit your post to remove the logically correct solution.]

--Mark

[GustavoB]

My not chip is:

CHIP NOT {
IN in;
OUT out;
PARTS:
Nand(a=in,b=in,out=out);
}

I've named exactly as the book. I would also like to add as evidence that the NOT chip worked perfectly in my AND chip.

[cadet1620]

Your chip is not named exactly as in the book. Your chip is named "NOT", all upper-case. The chip in the book is named "Not", capitalized case. You must also make sure that your file is named "Not.hdl" and not "NOT.hdl".

--Mark

[GustavoB]

I changed it:

CHIP Not {
IN in;
OUT out;
PARTS:
Nand(a=in,b=in,out=out);
}

And:

CHIP Or {
IN a,b;
OUT out;
PARTS:
Not(in=a,out=d);
Not(in=b,out=e);
Nand(a=d,b=e,out=out);
}

And it's still giving me the error.

[GustavoB]

Look:



I really have no idea on what I'm doing wrong. This seems similar to my AND chip but it's not working.

[Koen_Be3840]

What happens if you replace the two Nots by Nands in your Or Definition

[cadet1620]

Make sure that the test file you are loading is in the same directory as your Or.hdl.  From the screen shot, the Or.hdl that is loaded does not look like yours.  The one in the screen shot has spaces ahead of the IN and OUT ilnes and yours does not.

It looks like the test is loading the empty skeleton Or.hdl, and that does result in the test failing at line 3.

--Mark

[GustavoB]

cadet1620 wrote

Make sure that the test file you are loading is in the same directory as your Or.hdl.  From the screen shot, the Or.hdl that is loaded does not look like yours.  The one in the screen shot has spaces ahead of the IN and OUT ilnes and yours does not.

It looks like the test is loading the empty skeleton Or.hdl, and that does result in the test failing at line 3.

--Mark

It works when they're on the same directory. Weird... When I tested the AND chip, it worked perfectly even not being on the same directory.

[GustavoB]

It could work - I didn't test it - but it was weird because it wasn't working. I followed Mark's instruction and I got it done.

[GustavoB]

BTW, thanks for the help, guys. I'll delete the post in some hours.