Chapter 4 Help

[OrionMaster]

Can some one please explain to me how M,D,A and @value, work?

Thank You

[cadet1620]

OrionMaster wrote

Can some one please explain to me how M,D,A and @value, work?

Thank You

It might help to print figures 5.9 and 5.10 from chapter 5 and keep them handy as you study section 4.2.

The Hack computer has two registers, A and D. M acts like a register in the machine language syntax, but functionally it is the RAM memory cell located at the current value of the A register.

@nnn simply does A=nnn.

--Mark

[OrionMaster]

Thank you so much I get it  now.

[baylorfan]

When a C-instruction is used to store the computed value in both the A register and in M (i.e., in Memory[A]), which of the two A register values controls the memory location for the computed M?  In other words does the C-instruction use the the pre-staged address from the A-instruction (let's call it "staged-A"), or the new computed value stored in the A register (let's call it "computed-A")?  

It seems this would be controlled by the order in which the d-bits are processed, i.e., if destination A is processed before M, then the computed value is stored in the memory location of "computed-A", otherwise in that of "staged-A".

Please forgive me if this is spelled out somewhere in Chapter 4.

[cadet1620]

baylorfan wrote

When a C-instruction is used to store the computed value in both the A register and in M (i.e., in Memory[A]), which of the two A register values controls the memory location for the computed M?  In other words does the C-instruction use the the pre-staged address from the A-instruction (let's call it "staged-A"), or the new computed value stored in the A register (let's call it "computed-A")?  

It seems this would be controlled by the order in which the d-bits are processed, i.e., if destination A is processed before M, then the computed value is stored in the memory location of "computed-A", otherwise in that of "staged-A".

Please forgive me if this is spelled out somewhere in Chapter 4.

Short answer: "staged-A".

Welcome to the hardware world where all the instruction decoding happens in parallel; there is no "processing order" for the d-bits. This will make more sense after you've done chapter 5. Take a look at figure 5.9.

The Hack computer executes one instruction per clock cycle. During the execution of AM=A+1, the current value of the A register is driven onto the addressM bus and the output of the ALU (A+1 in this case) is driven onto the outM bus. The A-register's load and <writeM> are driven TRUE. This defines what is going to happen when the clock occurs: A+1 will be simultaneously stored into RAM[A] and A.

There is a related thread, Question regarding PC and ARegister, that talks about what happens with an instruction like A=M;JMP.

--Mark

[baylorfan]

Very helpful, Mark.   Thank you.