Chip Implementation

[rauls]

Good Morning,
To implement the "PARTS" is it necessary to draw the diagram of all the chips?
For example, would you need to draw the diagram of that chip before implementing it? And16 (a =, b =, out =);

Thank you!

[cadet1620]

You don't need to draw a diagram of the parts, but it can help you organize your thoughts for more complex chips.

For a chip like And16 where the implementation is straightforward—it is just 16 And chips collected into a single chip—you should not need to draw a diagram.

For a more complex chip like DMux4Way, a diagram can help you figure out how you can build it using 3 DMux parts.

--Mark

[rauls]

 
Got it,

Thank you very much!

[rauls]

8-way 16-bit multiplexor:
 * out = a if sel == 000
 *       b if sel == 001
 *       etc.
 *       h if sel == 111
 */

CHIP Mux8Way16 {
    IN a[16], b[16], c[16], d[16],
       e[16], f[16], g[16], h[16],
       sel[3];
    OUT out[16];

    PARTS:
     Mux4Way16(a=a ,b=b ,c=c ,d=d,sel=sel[0..1] ,out=w1 );
 

  Hello! I'm sorry
I read appendix A again. But, I did not find answers.
You can explain what that notation means "sel [0..1]". Because, when it comes to specifying bit on buses sel [1], I get it. In this case you are specifying a bit on the bus.
But, and so sel [0 ... 1] what exactly does this notation mean?

Thank you very much!


 

[cadet1620]

foo[a..b] means a bus consisting of bits a through b of bus foo.

In this case, Mux4Way16(sel=sel[0..1], ...); means a 2-bit bus made from bits 0 and 1 of the chip's sel input is connected to the Mux4Way16's 2-bit sel.

The bits match up from left to right, so if you use foo=bar[1..2] the the connections would be
    foo[0] = bar[1]
    foo[1] = bar[2]

--Mark

[rauls]

Got it.
Thank you