Johnaxle wrote
Wow. Did not understand much of the technical aspects of your answer but here's my rephrased question and I hope that's what you confirmed in your answer:
In one of your other answers in this topic, you say "So, for now at least, let's agree that the term "propagation delay" means the actual amount of time it takes for the output to change after the rising clock edge. Then pretty much by definition the output changes at the end of the propagation delay because that's what this agreed-to use of that term means. "
So if propagation delay is from the 50% of clock change to 50% of output change, then the output should not change at the end of the propagation delay, right? Because it has to change the remaining 50% to be at a valid logic level...
Notice that the statement, "'propagation delay' means the actual amount of time it takes for the output to change after the rising clock edge," is a qualitative statement only, and thus can't serve as a quantitative definition. It conveys the basic intent, but it lacks the unambiguous specificity for someone to actually make a measurement based on it. It takes a finite amount of time for the clock edge to rise. It takes a finite amount of time for the output to change. So where, exactly, would you start your time measurement and where, exactly, would you stop it? That isn't specified by that statement, so we need to clearly define what constitutes those events.
Whatever definition we eventually decide to use will have relatively little impact on the measurement because, in most logic families, those rising and falling edges, while not instantaneous, do not take very long.
Also, your last sentence might indicate a point that needs some clarification. When you say that the output has to change the remaining 50% to be at a valid logic level, that is not a true statement.
Each logic family has thresholds that constitute when, at a minimum, the device considers the input to be at a valid level. These are usually called Vil (which is the highest voltage that an input can be and be guaranteed of being recognized as a logic LO) and Vih (which is the lowest voltage that an input can be and be guaranteed of being recognized as a logic HI). Just pulling numbers for TI's SN74HC74 dual-DFF datasheet, when operating at a 4.5 V power supply, these are 1.35 V and 3.15 V, respectively.
In fact, the input likely never will get all the way to the supply voltage. When sourcing or sinking that maximum rated current (4 mA), this part's output is only guaranteed to get down to 0.33 V and up to 3.7 V. So if your timing is going to be based on it going from 0 V to 4.5 V, you're going to be waiting a long time.
Another point to consider. Let's say that we wanted to be hyper-pendantic and say that the propagation delay we from the time that the clock reached a valid HI level to when the output reached a valid logic level at its new state. We would have to shift the start of our timer from the 2.25 V level on the clock to 3.15 V (or 0.9 V higher) and we would need to shift the end of our timer from the 2.25 V level on the output to either 1.35 V or 3.15 V (or 0.9 V lower or higher). In both cases, the measurement is shifted to the right (slightly later moments in time). If they shift by the same amount, we end up with exactly the same measurement result. So the result will change only by the difference in how long it takes the clock to transition through that additional 0.9 V and how long it will take the output to transition through that additional 0.9 V. They are going to be pretty close to the same.
Finally, since we are talking about real devices operating in the real world, the variations from device to device, particularly over the temperature range they are designed to operate at, will completely swamp out these minor differences in measurement conventions.
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