Different bus widths error

[Uwarsta]

I find it weird that the only way (it seems) to pin single-bit pipe, for example, to And16 is to write a long and messy line like this:

And16(a=x, b[0]=notzx, b[1]=notzx, b[2]=notzx, b[3]=notzx, b[4]=notzx, b[5]=notzx, b[6]=notzx, b[7]=notzx, b[8]=notzx, b[9]=notzx, b[10]=notzx, b[11]=notzx, b[12]=notzx, b[13]=notzx, b[14]=notzx, b[15]=notzx, out=out);

All the while I can write b=true and the Hardware Simulator has no problem with that. I understand why functionality in b[0..x]=.. behaves the way it does but hey, no shortcut to connect 1 pin to every pin in 16-pin bus?

cadet1620 used a chip named Widen16 (http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/different-bus-widths-td3372452.html) just to around this nonsense. Additionally, can someone explain what he means by using TECS chips?

I have read the help pages of hml language but I cannot find a cleaner way to do this..

[cadet1620]

There is no way to directly connect a single bit signal to a bus. You must connect them one at a time like you did.

You can use a Mux16 in place of a Not16 and user-written part if you want to make the 16-bit notzx in line.
    Mux16(sel=zx, a=true, b=false, out=notzx16);

TECS (The Elements of Computing Systems) was the old name for the course, before it was rebranded Nand2Tetris.  The N2T chips would be just those chips defined in the book/course.

--Mark

[Uwarsta]

Thank you for the reply! I hope future Nand2Tetris homebrewers find this thread helpful. I certainly spent some four frustrating hours trying to figure out if there is a better way.

For the sake of learning (and Fun) I am trying to minimize the amount of gates that goes into the design, so I'll just keep the ugly line of code that I cobbled together.

[cadet1620]

Uwarsta wrote

For the sake of learning (and Fun) I am trying to minimize the amount of gates that goes into the design, so I'll just keep the ugly line of code that I cobbled together.

Optimizing for "part" count is indeed fun and educational, but it can easily be a false optimization.

For instance, the ALU's 'zr' can be generated with just 2 parts: an Add16 and a Mux.  Since the Add16 is the biggest and slowest part in the ALU, adding another Add16 nearly doubles the size and halves the speed of the ALU!

For your ugly line of code, here's a hint:
Multiplexors are amazingly versatile parts.  A mux with N select bits can implement any function of N variables, and about half of all functions of N+1 variables.  For example, here's Or(a, b):
    Mux(sel=a, a=b, b=true, out=out)

--Mark