Difficulties understanding latch circuits

[M.R.]

Hi, can someone explain to me how a SR Nor latch behaves when both inputs are 0,
without previous inputs/outputs? In what states are the outputs at the moment
you apply voltage to the circuit with both inputs being 0? Thank you in advance.

[cadet1620]

If both inputs are 0 then power is applied to an SR Nor Latch the latch comes up in a stable, but unknown state.

Strange analog things happen as the power supply voltage rises from 0 to operational voltage. The outputs will start climbing together, tracking a couple tenths of a volt below the power supply. Then one of the outputs begins to win the race and the other output drops back to near 0.

If you need to have your latch come up in a known state, you need to provide a power up reset signal and include it in one of the Nors.

Here's an image I just found. No details, but it looks like 2.5 volt CMOS. Power up followed by set then reset.



--Mark