Flexible RAM

[Krozu]

If you have a computer with a let's say, 32bit CPU, and everything works fine.
When you upgrade your computer to work with 64bit, but you decide to use your old RAM. How does this work exactly? Is the RAM designed to work with n-bit CPU's, or is the CPU built to deal with any kind of RAM?
If i were to try this with the CPU and RAM i made, my screen would probably start flashing red and swing its fist. My understanding of computer hardware is minimal to say the least, and this problem confuses me.

[cadet1620]

Krozu wrote

If you have a computer with a let's say, 32bit CPU, and everything works fine.
When you upgrade your computer to work with 64bit, but you decide to use your old RAM. How does this work exactly? Is the RAM designed to work with n-bit CPU's, or is the CPU built to deal with any kind of RAM?
If i were to try this with the CPU and RAM i made, my screen would probably start flashing red and swing its fist. My understanding of computer hardware is minimal to say the least, and this problem confuses me.

In a computer like a PC or Mac, there is a lot of circuitry between the CPU and the RAM. This includes things like the memory controller and cache RAM.

Cache RAM is there so that the CPU can get to commonly used data as fast as possible. Cache RAM is usually the same width as the CPU. System RAM can be various widths, and if necessary, multiple reads can occur to assemble the data into a CPU width word.  The CPU must be able to wait for the memory controller to do it's work.

One of the reasons for this is the speed of light limitation.  If the CPU is running at 1 Ghz, the cycle time is 1 ns (1x10^-9 s) in this time information can only travel 30 cm! The main memory may too far from the CPU for addresses to get to the RAM and data to get back before the CPU needs it.

--Mark

[Krozu]

That explained a thing or two, but gave me more questions than it did answers. (That's a good thing)

If i understand it right, the cache RAM you are talking about is L1-3 cache which is located on, but not really part of the CPU. And the memory controller turns 32bit data (if you have a 32bit system) into 64bit when writing to the RAM when its bus width is 64bits, and the other way around when reading from the RAM.

Or does it glue 2 32bits into 1 64bit... somehow? Tried to use my google-fu, but there isn't a huge amount of information about the memory controller.

As for the multiple reads, i guess this is where DDRx comes into play (or at the very least, shines)?

[cadet1620]

Krozu wrote

Or does it glue 2 32bits into 1 64bit... somehow? Tried to use my google-fu, but there isn't a huge amount of information about the memory controller.

Memory controller is a fairly generic term referring to the logic required to interface the CPU to the memory. You might have better luck searching for more specific things like "memory caching" and "virtual memory".  I'm not sure where the best place to get information about modern memory design is. It's a rather esoteric subject. You are getting deep into engineering.

Your best bet might be to look for datasheets on early Intel processors like the 80286 and 80386DX/SX which had relatively simple memory interfaces. IIRC, the 286 introduced protected addressing mode that supports virtual memory.

--Mark

[Dennis]

The memory/cache architecture of modern computers is indeed very dark magic. The Hack memory model is simple in this reguard becaus the RAM is only adressable in Blocks of 2 byte.

In contrast, on the x86 architektur (most common on desktop computers), the RAM is Byte adressable (from a assembler / programmer point of view), but the Memory is actually transfered in larger Blocks like 8 Bytes between the RAM and the slowest Cache. Hence, reading a 64 bit integer from the RAM takes one cyles if it's adress is a multiply of 8, but otherwise two since it's „crosses boundaries“. Lukily, the memory controller hides this complexity from the user of the machine.

But highly optimized real-world compilers takes this into account and try to »pack« structures as „block-friendly“ as possible, so that they »flow« through the cache chain as fast as possible. Here’s a more detailed description of this: Structure Member Alignment, Padding and Data Packing.

[Krozu]

Thanks for both reply's. Going to keep digging until i know what i want to know. Gonna require some brain bending and a big shovel.