While I was laying around ill last week I had an idea about how to turn the Hardware Simulator into a poor man's logic analyzer and be able to see what's happening in the asynchronous sequential circuits that lead up to the DFF.
By creating SNand (Sampled Nand) and SNot chips that are Nand and Not followed by a DFF one gets simulated propagation delay and periodic sampling. One can then cross-connect the SNands to make an RS Latch that can be simulated.
I wrote the HDLs for RS Latch, Clocked (Transparent) RS Latch, RS Flip-Flop and D Flip-Flop, and TST files to drive them, and wrote a few pages about them. The pages start at
http://www.marksmath.com/tecs/dffPlease take a look and let me know what you think. The later pages are pretty sparse at the moment. I think I'm going to find some interesting excerpts from the simulation outputs to annotate and add to the pages.
Comments and suggestions very much appreciated.
--Mark
Locked
