FullAdder

[Idrisadeniyi]

I started working on FullAdder chip but it is not working. Prof. Shimon mentioned that a FullAdder can be implemented using two HalfAdders' chip. When I finished the implementation using the two gates, I keep getting a comparison Failure at the final line. One thing I noticed however, is that, either the carry out pin or c input pin is not plugged. It is impossible for me to plug both using the two HalfAdders.

After a series of try and error, I logged into this forum to see if I would get some tips. And then I stumbled upon a conversation which suggests that a fullAdder could be implemented using 3 HalfAdders. It suggests that the operation should be done one after the other, just like one would do addition in decimal and the leading number would be carried to next position.

I have tried this method but it's not working. I keep getting comparison failure at different lines.

Below is what my hdl file look like:
HalfAdder(a=a, b=b, sum=s1, carry=cary1);
HalfAdder(a=s1, b=c, sum=s2, carry=cary2);
HalfAdder(a=cary1, b=cary2, sum=sum, carry=carry);

[WBahn]

Map out the math of what you are doing and you should see your mistake.

I'll try to do it here, but don't know if things will line up well

            a
            b
      --------
      cary1 s1
            c
      --------
      cary2 s2
--------------
carry sum

[Idrisadeniyi]

Thanks for pointing that out. I have identified my mistakes.
So I re-read your explanation to get it right. I now know that the sum of the first addition and the third pin will be added to get the final sum(I hope I got that right? ). What is still confusing, however, is the additioning /wiring of the 2weight bits. I know I have a first carry from the first addition and second carry from the second which I suppose are the 2 weight bits. If I add both of them such as:
HalfAdder(a=cary1, b=cary1, carry=carry); I still get a comparison failure at line 5.

[WBahn]

Look at the map more carefully. A Full Adder produces a two bit output. The least significant bit is the 'sum' output and the most significant bit is the 'carry' output.

So, from the map, when you add the two 'cary?' bits, which bit of the Full Adder output should be the final carry output? Keep in mind that the signal names in the map are simply the names used in your first part description).

By using three Full Adders you are essentially producing a three-bit output. But what is the largest result you can ever get from adding three one-bit numbers? What does that tell you about one of those three output bits?

[Idrisadeniyi]

I think this is getting more complicated for me as I can't wrap my head around it. If i use two HalfAdders, as in:
HalfAdder(a=a, b=b, sum=s1, carry=cary1);
HalfAdder(a=s1, b=c, sum=sum, carry=carry);

It will continue to produce the desired result until line 7 where I have combination of 1+1+0. Instead of producing sum=0 and carry=1, it will produce sum=0 and carry=0. And you could see that my cary1 part pin is useless because it's not connected to any pin.

And If I use three HalfAdders such as:
HalfAdder(a=a, b=b, sum=s1, carry=cary1);
HalfAdder(a=s1, b=c, sum=sum, carry=cary2);
HalfAdder(a=cary1, b=cary2);

This is my best attempt. I think you should be able to read from this what my confusion or lack of understanding really is.

[WBahn]

In your first attempt, notice that you don't use the carry signal (cary1) from the first Half Adder at all. That would only make sense if it can't have any impact on the result, but clearly it does. In the second attempt, you use the third Half Adder to add the carry signals from the other two, but then don't connect the outputs of that Half Adder to anything at all, so it might as well not be there. As a result, your overall carry signal for your Full Adder isn't connected to anything.

Personally, I think this should be treated as an error by the simulator. How it actually treats it is anyone's guess (which is why it should be treated as an error). Most logic simulators that don't treat unconnected signals as errors usually treat them as a logic LO (with no solid basis for doing so -- some real logic families, such as TTL, actually treat unconnected inputs as a logic HI, while other families, such as CMOS, can result in behavior that physically damages the chip) and I think this one is no different.

Again, go back to the math that is mapped out. Let's do it again, but this time use sn and cn as the sum and carry signals from Half Adder n.

       a
       b
---------
   c1 s1 (HA of a+b)
       c
---------
   c2 s2 (HA of c+s1)
---------
c3 s3    (HA of c1+c2)

The bottom entry in each column is the final result for that bit position, so we see that our final result is a three-bit value consisting of

c3 s3 s2

But we know that the largest value we can get by adding three 1-bit values is 011, so c3 will always be a zero and is not needed.

[Idrisadeniyi]

Thanks alot! I finally got it right. Your style of pointing out the errors gave me that drive to really work it out and think of additional recipe to arrive at the desired result. Thanks once more.

[WBahn]

No problem.

Now that you have a better understanding, see if you can figure out how to do the Full Adder using just two Half Adders and one more basic logic gate. The key is that you don't need the carry out from the third Half Adder.

Note that this is not required for the N2T project. Once you have a design that works, that's good enough. But looking at more efficient ways to implement logic is still a good learning exercise.

[Idrisadeniyi]

Alright. Thanks a lot