HDL implementation of Bit gate

[rick2047]

Hey,
I am trying to implement the HDL code for the bit gate. I am using the implementation in fig 3.1 as a reference. But I cannot get it to work. Actually I cannot understand how to clock the chips where does the CLOCKED keyword comes. this is what I have wrote so far



CHIP Bit {



    IN  in, load;

    OUT out;

   
    PARTS:
   

    Mux(a=in,b=out,sel=load,out=muxout);
    DFF(in=muxout,out=out);

}


but of course I cannot connect out to the input of Mux. How do I go about doing it.

[culchie]

You dont use the clocked keyword at all. It's inside the DFF chip and that makes this chip clocked.
Hint : As you say you can't put out into the input of the mux, but you can still put the output of the DFF into the input of mux

[rick2047]

The only way I see you can do it is by declaring a buffer gate, but we don't have one. Also it would be stupid to use two not gates. I really don't get it.

[ybakos]

If you follow the diagram in chapter 3, you'll figure it out.

[rick2047]

ybakos wrote

If you follow the diagram in chapter 3, you'll figure it out.

Actually I followed exactly that, In the diagram the out pin is connected back to the Mux and the second input of mux is the in bit. Load is used as the select bit. That's exactly what I wrote in the code

[rick2047]

I need to put the output of DFF into the mux that is clear. But I cannot possibly do that, then I need either a buffer or some fancy And-ing with true thing. But And-ing would be just HDL getting in my way. How do I do that. I hate it when the HDL comes into my way. Also I do not understand why I cannot just connect out to the input b of Mux. If I can do it in hardware (and it would work due to the clocked property of DFF) why not in the HDL. The HDL is supposed to reflect the hardware.

[ybakos]

>> But I cannot possibly do that

Yes... you can!

Review the HDL tips in the Appendix. In a nutshell, you can wire a chip's output to multiple internal pins that you create. For example, say I have a chip with input 'a' and output 'out':

SomeChip(in=someinput, out=outA,  out=outB);

You now have two internal pins called outA and outB.

Furthermore, there are additional errors in the HDL from your initial thread post. You have taken the declared output pin and are trying to wire it to the Mux's input.

Once you get things wired up legally, you'll be close. But remember, a Mux behaves in a certain way (the load bit causes either a or b being output) and you'll want to compare your wiring with the Bit specification.

Good luck! I know you can figure it out.

[rick2047]

Can someone please cut a .5 grade point for this. And ya I can figure out the other problem.

[David Rysdam]

SomeChip(in=someinput, out=outA,  out=outB);

You now have two internal pins called outA and outB.

Oooooooohhhhhhhhh!!!

[AntonioCS]

I stopped the reading of this book due to work/time issues and was now picking it up again. I couldn't make my bit implementation work.

I googled for the answer and was surprised to see that the path I was taking was almost correct (missed the or instruction).
In the illustration on page 43 we see that the DFF comes after the Mux but in hdl this will come first. I was doing so but was not really sure. I really hate it when the illustrations confuse me like this.

Hope I have better luck with the remaining chips.

Note: I haven't quite fully understood the implementation of this chip. I have reread chapter 3 a few times but I must be missing something obvious.

[cadet1620]

If you haven't already, read the Hardware Survival Kit, particularly the HDL Is Not A Programming Language section.

HDL is more like using a soldering iron to connect wires to parts to build a circuit.  It doesn't matter what order you list the parts in the HDL file.


On thing that might help to understand the Bit and other synchronous chips is to realize the the clock connected to the synchronous chips is the computer's instruction cycle clock; it ticks once per instruction executed by the computer.

The computer's CPU will decode the currently executing instruction and decide what needs to happen to various registers and set their in and load pins as needed.  Then the clock ticks and the registers store their new values and present them to the CPU to use for the next instruction.

--Mark

[linuxford]

AntonioCS wrote

I stopped the reading of this book due to work/time issues and was now picking it up again. I couldn't make my bit implementation work.

I think I read somewhere that the order that you list the PARTS doesn't matter.

I was able to get it to work by following the figure in 3.1 (1-bit register), in which you only need 1 MUX and 1 DFF for it to work, but there is something that I had to think about when I wired it up. When the load is 1 which MUX input pin (a or b) do I want to propagate through to the BIT 'out' pin.

By the way, the DFF is a primitive, built-in chip, so you don't need to make your own.

Hint: Notice in figure 3.1, that the MUX doesn't specify which pin is A and B. The part may be mirrored.