Hack actually a Harvard architecture (and not von Neumann per the book)?

[malyn]

Hello,

I have a question about the architecture of the Hack computer.  The Elements of Computing Systems is very consistent in describing Hack as a von Neumann machine, but to me Hack seems much more like a Harvard machine.


TECS describes the Hack architecture as follows:

- Section 5.2.2: [The Hack CPU] expects to be connected to two separate memory modules: an instruction memory ... and a data memory.

- Section 5.4: Unlike Hack, most general-purpose computers use a single address space for storing both data and instructions.


Per Wikipedia, the von Neumann architecture is described as follows:

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The von Neumann architecture is a design model for a stored-program digital computer that uses a central processing unit (CPU) and a single separate storage structure ("memory") to hold both instructions and data.
---

That description is in conflict with much of Chapter 5, which states that Hack uses separate address spaces for Instructions and Data.


The Harvard architecture, on the other hand, does seem to accurately describe Hack:

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The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data.
---

The diagram at the top of that article is almost identical to figure 5.10 ("Proposed implementation of the topmost Computer chip") in TECS.  As an aside, figure 5.1 is an accurate depiction of the von Neumann architecture, but figures 5.1 and 5.10 do not appear to describe the same thing (5.1 is von Neumann, 5.10 is Harvard).


Am I misunderstanding the von Neumann and Harvard architectures or is there something about the Hack architecture that does make it a von Neumann machine even though it appears to have separate Instruction and Data memory?

Thank you for your time!

[ybakos]

I'd love to discuss this further. When I worked through TECS I also had some misgivings about the fact that ROM was separate from RAM... and hence is it really a true Von Neumann machine?

[cadet1620]

I've done a bit of research.  This seems to be an academic culture issue.

In 1945 John von Neumann wrote "First Draft of a Report on the EDVAC,"[1] which for the first time described a stored program computer.  This computer did not have a unified code and data memory.

In 1946 he co-authored "Preliminary Discussion of the Logical Design of an Electronic Computing Instrument,"[2] which described a machine that required code memory to be changeable under program control; their implementation was to unify code and data memory.

Some people, therefore, use "von Neumann architecture" to refer to any stored program computer, while others use it to refer to stored program computers with unified code and data memory.  In fact, you can find both usages in different Wikipedia articles!

University of Colorado in the mid 70's was teaching the latter, so that's what's burned into my brain's ROM and caused me some cognitive dissonance while I was reading TECS.

So the answer to whether Hack is a von Neumann architecture is that it depends upon where you went to school.

--Mark

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[1] von Neumann, John (1945), "First Draft of a Report on the EDVAC," 47 pages, Moore School of Electrical Engineering, University of Pennsylvania, Philadelphia, June 30 1945.
(http://www.virtualtravelog.net/entries/2003-08-TheFirstDraft.pdf 24 Nov 2010)

[2] Burks, Arthur W., Goldstine, Herman H., and von Neumann, John (1946), "Preliminary Discussion of the Logical Design of an Electronic Computing Instrument," 42 pages, Institute for Advanced Study, Princeton, New Jersey, June 1946, 2nd edition 1947.
(http://preview.tinyurl.com/vonneumann-pdf 24 Nov 2010)

[Matt]

I think most computers these days have split cache (instruction cache and data cache), which are loaded from main memory which is not split. So if you look at it from the perspective of outside the CPU it is von Neumann.

I believe it is a pretty simple task to convert the split setup into a single memory design, but it would be a bit slower. I think this is why most modern cpu's implement a split cache design.

[cadet1620]

Matt wrote

I think most computers these days have split cache (instruction cache and data cache), which are loaded from main memory which is not split. So if you look at it from the perspective of outside the CPU it is von Neumann.

There are some strange processors out there!

A device I was writing firmware for a year or so ago used a PIC24FJ256GB110 microcomputer.  This beast has 24-bit instruction memory (flash ROM) and 16-bit data memory.  There is a strange mapping mode that presents the program memory in the data memory address space.  You get 3 bytes of ROM, a zero, 3 bytes of ROM, a zero, etc.  Makes it a bit strange to get string constants stored in the flash.  Fortunately, the compiler dealt with it so I didn't have to.  You can erase and reprogram blocks of flash under program control.  (You'd best not be running in the block you erase!)

I believe it is a pretty simple task to convert the split setup into a single memory design, but it would be a bit slower. I think this is why most modern cpu's implement a split cache design.

I have in fact done this.  See my post HACK II: Escaping the Harvard straitjacket and my web site http://www.marksmath.com/tecs/hack2 for a modified Hack computer that will run on the Hardware Simulator.  For all normal instructions it runs just like Hack, one clock per instruction.  An extra cycle is added only for instructions that access the program memory.

--Mark