HackCPU and DATA bus architecture

[clinden]

Hi,

I grew up with Z80 CPUs and Assembler. I worked on a Amstrad CPC and as any other computer I could get my hand on it actually have a data bus instead of a read and write bus to memory.

I now have issues:
1. In real world no RAM with separated input and output exist. They have been optimized to have a bus and either output data or input data from that bus.
2. The CPU and all other Chips that require data transfer are all connected to the same data bus and specific logic regulates who reads and who writes on the bus to avoid conflicts and jams. More complicated designs will get more and more complicated because of this design.

So my questions are:
1. What was the design principles to not design a bus structure.
2. How could I build that in HDL if at all? A RAM chip having input and output data lines shared with an additional read/write line would do it, but I would need to define a chip where input line and output lines are the same. (my fear is I will never be able to, because the limit of input cannot be output at the same time in the HDL simluator you used).

[WBahn]

The biggest reason is almost certain that bidirectional data buses can't be supported using a NAND-only architecture, you need a means to place the various device drivers into a high-Z state.

On top of that, bidirectional buses would considerably complicate the hardware implementation and require the student to delve too deep into one aspect of a course that, by its nature, has to sacrifice depth across the board in order to support the enormous breath. Compromises have to be made.

Furthermore, while shared I/O data buses are the most common, architectures with separate buses also exist. RAM architectures with multiple address and separate I/O exist, such as Dual Port RAM. Sometimes one of the ports is bidirectional and other times it isn't.

Common uses of multiport RAM are for device memory (such as video RAM). Also, the register space on a CPU is usually multiport.

Since the Hack uses memory-mapped I/O, it makes sense to make that dual port. Also, since the Hack only has a single general purpose CPU register, having the RAM have separate read and write ports gives a bit greater power to the instruction set while keeping it small and simple.

[clinden]

Thanks for the insights.

Now I need to find a good source explaining how that is done in VHDL ... as all this course here has for me the purpose to get into VHDL for FPGA programming.

Thanks
Christoph