Hardware simulator is sensitive to ordering of HDL statements.

[Will Marrero]

Appendix 2 of the book states that HDL statements can be reordered without affecting the chip's behavior, however the online hardware simulator tool seems to be sensitive to the ordering of statements.  I was having difficulty passing the tests for the CPU chip I implemented and was confused by the output that was generated.  By changing the order of the statements in the PARTS section, I was then able to pass the tests.

A thread where I posted a screenshot of the simulator with what seems to be inconsistent output in the ALU visualizer can be found here: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Confused-with-simulator-output-on-CPU-td4037903.html

[yonlap]

Encountered this as well very early in the course. Is this being addressed? I posted an example here