Have problem with my pc.hdl

[Chen Li]

/**
 * A 16-bit counter with load and reset control bits.
 * if      (reset[t] == 1) out[t+1] = 0
 * else if (load[t] == 1)  out[t+1] = in[t]
 * else if (inc[t] == 1)   out[t+1] = out[t] + 1  (integer addition)
 * else                    out[t+1] = out[t]
 */

CHIP PC {
    IN in[16],load,inc,reset;
    OUT out[16];

    PARTS:
    // Put your code here:
    Mux16(a = o1, b = false, sel = reset, out = o0);
    Register(in = in, load = load, out = o1);
    Inc16(in = o1, out = o2);
    Mux16(a = o1, b = o2, sel = inc, out = o3);
    Mux16(a = o3, b = o0, sel = reset, out = out);
}

Here is my implementation and I select MUX16 as the fial chip to output result. I cannot figure out what's wrong. Thanks in advanced.

[cadet1620]

Think about when you made Bit. Because changes in Bit's 'in' and 'load' must not affect Bit's 'out' until the clock occurrs, all the logic controlled by Bit's inputs had to be on the input side of the DFF.

PC needs the same general structure as Bit: logic controlled by its inputs feeds a storage element that directly connects to the output, and also feeds back to the input control logic.

Did you notice that by tying the Register's load=true, you logically turned Register into a DFF16?

[Chen Li]

Thanks for your inspiration, Mark! I have figured out where I go wrong and have passed all tests, here is my implementation:

//removed


If possible, can you provide me other awesome solutions(iirc, you mentioned pc.hdl have many different solutions, even using ALU, I think it is a good time to understand these chips deeper), thanks,

-- Chen Li
-- mail: [e-mail]

[cadet1620]

Please edit your post to remove the working HDL. We want students to develop their own solutions.

I'll answer you shortly by email.

--Mark