# Hello everybody, and thanks for the help!

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## Re: sorry i forget about mux16

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## Re: sorry i forget about mux16

 This post was updated on . hello yes i simulate, is working perfect here my HDL CHIP ALU {     IN           x[16], y[16],  // 16-bit inputs                 zx, // zero the x input?         nx, // negate the x input?         zy, // zero the y input?         ny, // negate the y input?         f,  // compute  out = x + y (if f == 1) or out = x & y (if == 0)         no; // negate the out output?     OUT         out[16], // 16-bit output         zr, // 1 if (out == 0), 0 otherwise         ng; // 1 if (out < 0),  0 otherwise     PARTS:         // code snipped by admin (it served its purpose) } so here i use 6 MUX
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## Re: sorry i forget about mux16

 Administrator michael1978 wrote hello yes i simulate, is working perfect here my HDL CHIP ALU {     IN           x[16], y[16],  // 16-bit inputs                 zx, // zero the x input?         nx, // negate the x input?         zy, // zero the y input?         ny, // negate the y input?         f,  // compute  out = x + y (if f == 1) or out = x & y (if == 0)         no; // negate the out output?     OUT         out[16], // 16-bit output         zr, // 1 if (out == 0), 0 otherwise         ng; // 1 if (out < 0),  0 otherwise     PARTS:        // code snipped } so here i use 6 MUX It's perfectly reasonable to use 6 Muxes here. It's not necessary and an actual implementation likely wouldn't, but especially for this project where matching the implementation to the conceptual model has value, it's perfectly legitimate. In practice, if you want to either pass a signal or zero it you simply pass it through an AND gate with a control signal going to the other input. If you want to either pass or invert it, you simply pass it through an XOR gate with a control signal going to the other input.
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## Re: sorry i forget about mux16

 hello....thnx for answer but i dont understand you so good is here posibble to reduce use of mux ic?
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## Re: sorry i forget about mux16

 Administrator michael1978 wrote hello....thnx for answer but i dont understand you so good is here posibble to reduce use of mux ic? It's always possible to reduce the use of the Mux part -- If nothing else, you can always implement it using nothing but two-input Nand gates. There are usually multiple ways to accomplish any task (unless it's super simple) and there are likely more than one that are perfectly reasonable. In this case, let's look at just the portion where we want to use the zx signal to either pass the X input to the next part or pass a LO signal on all sixteen bits. Conceptually, using the zx signal as the channel-select input to a Mux that chooses either the X-input or a static LO is perfectly reasonable since it matches the goal we are trying to achieve extremely well. But let's consider an alternative. Take just the lsb of the X-input and apply it to one input of an And gate. Now take the zx signal and complement it (pass it through a Not gate) to get a signal (let's call it zxb) and apply that to the other input of the And gate. Notice that if zx is LO (making zxb HI) then the output of the And gate is the same as the lsb of the X-input; but if zx if HI (making zxb LO) then the output of the And gate is LO regardless of the value of the lsb of the X-input. Now just do the same thing for each of the sixteen bits of the X-input (applying each bit to one input of an And gate and applying the same zxb signal to the other). Can you see how you can do something similar to implement the nx functionality using Xor gates instead.
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## Re: sorry i forget about mux16

 hello sir, thanks and i did in logisim, the zx but again i have to use 4 AND gat and 4 NOT gate, you know, why i say because cadet1620 he use LESS IC, how he did it, i dont know,
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## Re: sorry i forget about mux16

 Administrator michael1978 wrote hello sir, thanks and i did in logisim, the zx but again i have to use 4 AND gat and 4 NOT gate, you know, why i say because cadet1620 he use LESS IC, how he did it, i dont know, WHERE in the design are you talking about???? If you are talking about inside the ALU, then keep in mind that cadet1620's schematic (in Post #2 of this thread) shows the entire ALU as a single chip, so you can't see how many gates he used for it. If you are referring to a design he has for the ALU in some other thread, then please include a link to the post containing the schematic. I'm not a mind reader. Also keep in mind that the ICs he used are multi-gate packages. Each 74LS08 contains four 2-input AND gates while a 74LS10 contains three 3-input NAND gates. If you want to understand his design for the CPU, then start by identifying the main functional components. The ALU is easy to spot. Next identify the A register and the D register. Then identify the program counter. Then identify the Mux that controls which data gets sent to the A register and the Mux that controls which data gets sent to the Y-input of the ALU. Pretty much everything that is left is the instruction decode logic.