Help implement cpu.hdl

[shaheemppp]

Its been days since started implementation, but every time it fails test ,i dont know what to do next, can someone help me to fix the flaws.
 


    PARTS:
    //instruction handling
    Mux16(a=instruction , b=aluout , sel=instruction[15] , out=insORalu );

    //A register
    And(a=instruction[15] , b=instruction[5] , out=arload );
    Register(in=insORalu , load=arload , out=arout , out[0..14]=addressM );

    //D register
    And(a=instruction[15] , b=instruction[4] , out=drload );
    Register(in=aluout , load=drload , out=drout );

    //ALU second input decider
    And(a=instruction[15] , b=instruction[12] , out=aORmload );
    Mux16(a=arout , b=inM , sel=aORmload , out=aORm );

    //ALU
    And(a=instruction[15] , b=instruction[11] , out=zxin );
    And(a=instruction[15] , b=instruction[10] , out=nxin );
    And(a=instruction[15] , b=instruction[9] , out=zyin );
    And(a=instruction[15] , b=instruction[8] , out=nyin );
    And(a=instruction[15] , b=instruction[7] , out=fin );
    And(a=instruction[15] , b=instruction[6] , out=noin );

    ALU(x=drout , y=aORm , zx=zxin , nx=nxin ,
    zy=zyin , ny=nyin , f=fin , no=noin ,out=aluout,
    out=outM , zr=zrout , ng=ngout );

    //writeM
    And(a=instruction[15] , b=instruction[3] , out=writeM );

    //pc load
    Nand(a=zrout , b=ngout , out=JGT );  //JGT
    Or(a=JGT , b=zrout , out=JGE );        //JGE
    Not(in=zrout , out=JNE );                  //JNE
    Or(a=ngout , b=zrout , out=JLE );      //JLE
   
    And(a=instruction[15] , b=instruction[0] , out=sel0 );
    And(a=instruction[15] , b=instruction[1] , out=sel1 );
    And(a=instruction[15] , b=instruction[2] , out=sel2 );

    Mux8Way16(a[0]=false , b[0]=JGT , c[0]=zrout , d[0]=JGE ,e[0]=ngout ,f[0]=JNE,
    g[0]=JLE , h[0]=true , sel[0]=sel0,sel[1]=sel1,sel[2]=sel2 , out[0]=pcload);

    //program counter
    PC(in=arout , load =pcload , inc=true , reset=reset , out[0..14]=pc );

[dolomiti7]

One thing that pops into my eyes is that in case of an A instruction bit 15 is 0. It appears that you are loading A when bit 15 is 1?!

Another observation: you are masking the ALU control bits in case of an A instruction. That is unnecessary since the output of the ALU will only be loaded into registers if the respective control bits are set. So the ALU output in case of an A instruction is meaningless and will just be ignored.

[shaheemppp]

thank you for that.
I see less differences now but still exists. most of them is due to D register being zero,i dont understand why
D register value is not loading.

[dolomiti7]

In order for the hardware simulator to recognise which register is your D register, you are supposed to use the internal part DRegister instead of your standard Register. Same goes for ARegister, however that is not necessary to pass the test since only the output address pins are compared, and not the A register itself. I believe that is mentioned in the book and the slides?

Please note that the online hardware simulator still seems to be sensitive to the order of the HDL instructions in some cases. You may want to check the old Java based tools to verify instead.