How does ALU not feedback when storing results?

[sectrix]

For a fun project, I've been building a computer based on this book in a videogame. I've got the CPU and some ROM and RAM all wired up, and have recently started testing.

When I began testing the various ALU functions, I realized I have no idea how this should work properly.

For example, let's say I want to compute a sum and store it somewhere. I load one operand into A, then use the ALU to transfer it to D. Then load the second operand into A. Then tell the ALU to compute the sum of A and D and store the output in D. Since D is also one of the operands, and the ALU is a purely sequential circuit, won't the ALU keep adding the result back into the sum (until the next clock)?

In other words, how can the operand and the result of an operation be stored in the same location without feeding back into the operation?

[cadet1620]

sectrix wrote

For example, let's say I want to compute a sum and store it somewhere. I load one operand into A, then use the ALU to transfer it to D. Then load the second operand into A. Then tell the ALU to compute the sum of A and D and store the output in D. Since D is also one of the operands, and the ALU is a purely sequential circuit, won't the ALU keep adding the result back into the sum (until the next clock)?

Where you are saying A and D, you should be saying A Register and D Register. The registers are the sequential part of the circuit that keeps the feedback from happening.

I'll take a shot in the dark here. Assuming that you have A and D registers in your (minecraft?) CPU, but are experiencing this feedback problem, the registers are probably "level triggered" instead of "edge triggered."

Level triggered means that the register output follows the register input while the clock is high and stores the data when the clock is low.

Check out http://play-hookey.com/digital/sequential/. Level triggered is the "D Latch", edge triggered is the "D Flip-Flop".

If your registers (and RAM) are level triggered, it might be easiest to make them edge triggered by putting two of them in series, the first one connected to ~CLK and the second to CLK.

--Mark

[sectrix]

Ahh, I think I see. If writing to the registers and RAM is edge triggered, it will only enable write for a brief moment after the data is on the line and before the resulting output propagates back to the input. So in my addition example, the sequence could be:
- High clock: PC at 0, first number appears on A register inputs
- Falling
- Low clock
- Rising: A register write pulses
- High clock: PC at 1, ALU connects A register outputs to D register inputs
- Falling
- Low clock
- Rising: D register write pulses

... and so on. Correct?
If this is the case, does it matter if I trigger on the rising or falling edge?

Also, thanks for the quick reply. And for the 'Ah ha!' moment.

PS: Actually this is for a game called Starbound. It is similar to Minecraft, but is a 2D sidescroller.

[cadet1620]

sectrix wrote

... and so on. Correct?
If this is the case, does it matter if I trigger on the rising or falling edge?

Correct, with some caveats for real world circuits because electronics is not instantaneous:
  o  The data must be present and stable for a small amount of time before the clock edge, this is called setup time,
  o  The data must remain stable for a small amount of time after the clock edge, this is called hold time.
Violating the setup and hold times can cause very strange things to happen.

It does not matter which clock edge you use as long as you are consistent.  It's common in real world computers to have multiple clock phases (same frequency, but offset from each other in time) so that setup and hold times can be honored.

Example: in the Hack computer the A register output is used to load the PC when jumps occur.  Both these parts trigger on same clock edge, so there is possibility for insufficient hold time for the PC's data input.

Very common is to have a 2 phase clock

By using rising and falling edges of CLK1 and CLK2 you get 4 distinct times during the clock cycle when you can trigger synchronous logic.

I hope this is helpful, I expect that you may need to deal with setup time issues in your game environment.

PS: Actually this is for a game called Starbound. It is similar to Minecraft, but is a 2D sidescroller.

I'll have to check it out...

--Mark

[sectrix]

Thank you, yes, you've been most helpful.

For my situation, simply pulsing the write enable (I'm limited to gated-d latches unless I build my own from basic gates) solved the timing issue. I tested addition, AND, subtraction, jumps, and moving data between registers and RAM, and it all works perfectly. I'll probably attempt the phased clock for version 2, after I've made some optimizations and/or figured out how to make an equally capable ALU in an 8-bit version.