How to connect internal labels to output pins?

[sakumar]

The "out" pins of the ALU are connected to the cpu "outM" and also feed back to the D and A registers.

But if in HDL I connect the ALU "out" directly to the CPU "outM", then the simulator will complain if I connect "outM" to the input of A-register or D-register.

One solution I have is to connect the ALU "out" to a new internal label (let's say "foo") and then connect "foo" to the input of D-Register and A-register.

But then how to connect "foo" to "outM"? I have been using a dummy Or16 with one input as "foo" and the other input as false and the "out" of Or16 as "outM".

While this works, it seems to me I am wasting gates here. Is there an HDL syntax to connect internal labels to output labels without having to use dummy Or gates? Or is it the case that the dummy Or16 is actually needed?

I feel like I am missing something here and would appreciate some clarification. Thanks.

[sakumar]

Related, question (I think). Why is the decode module needed? Can't I directly use instruction[15] for i-bit etc.?

[cadet1620]

See example in A.5.3. Note that you can have more than one connection to a part's output pins.

--Mark

[cadet1620]

sakumar wrote

Related, question (I think). Why is the decode module needed? Can't I directly use instruction[15] for i-bit etc.?

Some of the control signals should only be active during one type of instruction or the other. For example, writeM better not happen during an @ instruction. Note that you don't need to make a "decode" chip; the instruction decode is part of the CPU.

--Mark

[sakumar]

Thanks! I didn't spot that bit of subtlety in the HDL syntax -- that the pins of a chip can be given multiple labels.

Can I do the same thing when specifying the Mux whose input is instruction[0..15]? Just give new labels to instruction as i, a, c, d, j?

[sakumar]

cadet1620 wrote

Some of the control signals should only be active during one type of instruction or the other. For example, writeM better not happen during an @ instruction. Note that you don't need to make a "decode" chip; the instruction decode is part of the CPU.

That was my question, I guess. That the grey box labeled "decode" in figure 5.9 wasn't an active chip like the other grey boxes/triangles/trapezoid in the figure. It seems to me I just need to re-label the bits in instruction[0..15] for convenience.

[sakumar]

sakumar wrote

That was my question, I guess. That the grey box labeled "decode" in figure 5.9 wasn't an active chip like the other grey boxes/triangles/trapezoid in the figure. It seems to me I just need to re-label the bits in instruction[0..15] for convenience.

I realized that my thinking is a bit muddled here. One could view "decode" as the collection of individual bits of logic representing the various circle-Cs in Figure 5.9.