How to ng and zr?

[kingofbuffs]

So, I implemented my ALU, and suprisingly, it was rather easy and took me a short time to do it. <solution snipped> I don't think this is an elegant solution but it passes the nostat test.

However, I am having a hard time with ng and zr. Here's what I have been able to figure out so far:
If I check the first bit of the output, and if it is 1, then ng is 1. Something like if out[0] = true, then ng=true.

This is rather hard to implement since it's not possible to connect output to anywhere.

And for zr, if the whole output is zero, then zr is 1. If out[0..15]=false, then zr=1. I think this one is doable with an AND gate but then again, it's impossible to connect the output to anywhere.

Any suggestions as to how I can tackle this problem? I feel like I am close to the answer.

Any help is appreciated.

[WBahn]

Please don't post solutions -- let others learn by struggling with it the same you you did.

[WBahn]

kingofbuffs wrote

However, I am having a hard time with ng and zr. Here's what I have been able to figure out so far:
If I check the first bit of the output, and if it is 1, then ng is 1. Something like if out[0] = true, then ng=true.

This is rather hard to implement since it's not possible to connect output to anywhere.

And for zr, if the whole output is zero, then zr is 1. If out[0..15]=false, then zr=1. I think this one is doable with an AND gate but then again, it's impossible to connect the output to anywhere.

Any suggestions as to how I can tackle this problem? I feel like I am close to the answer.

Any help is appreciated.

Not quite sure what you mean by it not being possible to connect output to anywhere. Output of what? The part as a whole?

Remember that you can use the output of a part many times. So you can do things like

And(a=fred, b=sue, out=tim, out=tom);

Also, give some more thought to how you are going to use that And gate to get zr. You're not far off, but not quite there.

[kingofbuffs]

Apologies, I thought it would be fine if I put it in a link.

I didn't realize you could have different outputs with different names. It's a little odd, since And gate is supposed to have only one output, so it didn't really dawn on me.

For ng I am using the 2's complement rule, written in the book: "The codes of all negative numbers begin with a 1". So, if I could just check if the first bit is a 1, that would solve it.

Going with your example,
And(a=fred, b=sue, out=tim, out=tom);
And(a=tom[0], b=true, out=ng);

This seems like it should work but it throws an "sub bus of an internal node may not be used" error. I don't really understand this, since I feel like it should be possible to use a sub bus of a given output.

(I wrote a paragraph explaining my thought process as to how I was planning on finding zr, only to realize I read your reply wrong. In the end, I found  the solution.)

[WBahn]

kingofbuffs wrote

Going with your example,
And(a=fred, b=sue, out=tim, out=tom);
And(a=tom[0], b=true, out=ng);

This seems like it should work but it throws an "sub bus of an internal node may not be used" error. I don't really understand this, since I feel like it should be possible to use a sub bus of a given output.

One odd peculiarity of this HDL simulator is that ONLY the input and output signals can have sub busses. That's why you can use the ports multiple times.

What's the point of trying to use tom[0]. In my example, tom is just a single wire connected to a particular single-wire pin of an And gate. If you wanted that to go to a single-wire output of the chip, then just do that:

And(a=fred, b=sue, out=tim, out=ng);

(I wrote a paragraph explaining my thought process as to how I was planning on finding zr, only to realize I read your reply wrong. In the end, I found  the solution.)

This is often the way it goes. The reason is that, in explaining our thought process to someone (or something) else, we are forced to really consider what it is we are doing in a greater level of detail than when it was just an idea running around in our mind. By rights, I should have one of the most educated dogs that's ever existed, given how many things I've explained to that mutt. Another way is to write detailed documentation comments explaining exactly how your code works -- if it's giving you problems, assume it's going to give whoever is reading your code ten years from now problems and you have explain exactly how it works step by step. In the process, you'll frequently stop yourself, slap your head, and go fix the problem.

[kingofbuffs]

I must have misread your reply, sure if tom is single wire, there's no point.

However, If tom = 1111 1111 1111 1111, then I could check the first bit and go from there.

Anyway, with your tip, I found ng. But, it just kept  throwing comparison failures at line 14, apparently zr wasn't working properly.

I spent a long time trying to figure this out. Namely, how exactly could I turn 16 bit input into one bit output. Figuring out if the output is all 0s is easy, but channeling it to zr was unexpectedly hard. By the end I was so frusturated, I created this abomination. (w1 is the whole output) This works, but honestly, I would prefer if it didn't. I feel like I am missing something very simple and on the nose.

This reminds me of the time when my math teacher told me that I had no imagination because I wrote a page long solution to a simple problem.

Thank you so much for taking the time to help me WBahn, I really appreciate it.

 

[WBahn]

kingofbuffs wrote

I must have misread your reply, sure if tom is single wire, there's no point.

However, If tom = 1111 1111 1111 1111, then I could check the first bit and go from there.

But tom HAS to be a single-wire output because it is connected to the output of an And gate, which is a single-wire output. They HAVE to match!

Anyway, with your tip, I found ng. But, it just kept  throwing comparison failures at line 14, apparently zr wasn't working properly.

I spent a long time trying to figure this out. Namely, how exactly could I turn 16 bit input into one bit output. Figuring out if the output is all 0s is easy, but channeling it to zr was unexpectedly hard. By the end I was so frusturated, I created this abomination. (w1 is the whole output) This works, but honestly, I would prefer if it didn't. I feel like I am missing something very simple and on the nose.

This reminds me of the time when my math teacher told me that I had no imagination because I wrote a page long solution to a simple problem.

Thank you so much for taking the time to help me WBahn, I really appreciate it.

Your basic approach is correct, but you are reinventing the wheel. You can do this task with four parts. Take a look at the inventory of parts you built in Chapter 2. There's a very specific reason some of the parts of individual inputs while others have bused inputs.