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Hi,
I am stuck at how to use a specific bit 'a', 'b' and so on for Dmux8Way. The syntax is very confusing, both in HDL survival guide and the appendix.
What am I doing wrong in the following? I am repeatedly getting the error, "sub-bus of an internal node may be used..." or after tweaking, "specified sub-bus not in range...".
Finally, assuming my implementation is correct, when load=1, the addressed register gets the value of 'in'. Now, won't the value for the seven non-addressed registers be overwritten by 0000 in this case?
//My code, I even tried a=regIn[0], b=regIn[0] and so on
DMux8Way(in=in[0], sel=address, a[0] =regIn0, b[0] =regIn1, c[0] =regIn2, d[0] =regIn3, e[0] =regIn4, f[0] =regIn5, g[0] =regIn6, h[0] =regIn7);
DMux8Way(in=in[1], sel=address, a[1] =regIn0, b[1] =regIn1, c[1] =regIn2, d[1] =regIn3, e[1] =regIn4, f[1] =regIn5, g[1] =regIn6, h[1] =regIn7);
DMux8Way(in=in[2], sel=address, a[2] =regIn0, b[2] =regIn1, c[2] =regIn2, d[2] =regIn3, e[2] =regIn4, f[2] =regIn5, g[2] =regIn6, h[2] =regIn7);
DMux8Way(in=in[3], sel=address, a[3] =regIn0, b[3] =regIn1, c[3] =regIn2, d[3] =regIn3, e[3] =regIn4, f[3] =regIn5, g[3] =regIn6, h[3] =regIn7);
DMux8Way(in=in[4], sel=address, a[4] =regIn0, b[4] =regIn1, c[4] =regIn2, d[4] =regIn3, e[4] =regIn4, f[4] =regIn5, g[4] =regIn6, h[4] =regIn7);
DMux8Way(in=in[5], sel=address, a[5] =regIn0, b[5] =regIn1, c[5] =regIn2, d[5] =regIn3, e[5] =regIn4, f[5] =regIn5, g[5] =regIn6, h[5] =regIn7);
DMux8Way(in=in[6], sel=address, a[6] =regIn0, b[6] =regIn1, c[6] =regIn2, d[6] =regIn3, e[6] =regIn4, f[6] =regIn5, g[6] =regIn6, h[6] =regIn7);
DMux8Way(in=in[7], sel=address, a[7] =regIn0, b[7] =regIn1, c[7] =regIn2, d[7] =regIn3, e[7] =regIn4, f[7] =regIn5, g[7] =regIn6, h[7] =regIn7);
DMux8Way(in=in[8], sel=address, a[8] =regIn0, b[8] =regIn1, c[8] =regIn2, d[8] =regIn3, e[8] =regIn4, f[8] =regIn5, g[8] =regIn6, h[8] =regIn7);
DMux8Way(in=in[9], sel=address, a[9] =regIn0, b[9] =regIn1, c[9] =regIn2, d[9] =regIn3, e[9] =regIn4, f[9] =regIn5, g[9] =regIn6, h[9] =regIn7);
DMux8Way(in=in[10], sel=address, a[10]=regIn0, b[10]=regIn1, c[10]=regIn2, d[10]=regIn3, e[10]=regIn4, f[10]=regIn5, g[10]=regIn6, h[10]=regIn7);
DMux8Way(in=in[11], sel=address, a[11]=regIn0, b[11]=regIn1, c[11]=regIn2, d[11]=regIn3, e[11]=regIn4, f[11]=regIn5, g[11]=regIn6, h[11]=regIn7);
DMux8Way(in=in[12], sel=address, a[12]=regIn0, b[12]=regIn1, c[12]=regIn2, d[12]=regIn3, e[12]=regIn4, f[12]=regIn5, g[12]=regIn6, h[12]=regIn7);
DMux8Way(in=in[13], sel=address, a[13]=regIn0, b[13]=regIn1, c[13]=regIn2, d[13]=regIn3, e[13]=regIn4, f[13]=regIn5, g[13]=regIn6, h[13]=regIn7);
DMux8Way(in=in[14], sel=address, a[14]=regIn0, b[14]=regIn1, c[14]=regIn2, d[14]=regIn3, e[14]=regIn4, f[14]=regIn5, g[14]=regIn6, h[14]=regIn7);
DMux8Way(in=in[15], sel=address, a[15]=regIn0, b[15]=regIn1, c[15]=regIn2, d[15]=regIn3, e[15]=regIn4, f[15]=regIn5, g[15]=regIn6, h[15]=regIn7);
Register(in=regIn0, load=load, out=regOut0);
Register(in=regIn1, load=load, out=regOut1);
Register(in=regIn2, load=load, out=regOut2);
Register(in=regIn3, load=load, out=regOut3);
Register(in=regIn4, load=load, out=regOut4);
Register(in=regIn5, load=load, out=regOut5);
Register(in=regIn6, load=load, out=regOut6);
Register(in=regIn7, load=load, out=regOut7);
Mux8Way16(a=regOut0, b=regOut1, c=regOut2, d=regOut3, e=regOut4, f=regOut5, g=regOut6, h=regOut7, sel=address, out=out);
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Administrator
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DMux8Way(in=in[0], sel=address, a[0] =regIn0, b[0] =regIn1, c[0] =regIn2, d[0] =regIn3, e[0] =regIn4, f[0] =regIn5, g[0] =regIn6, h[0] =regIn7);
The specific problem here is that the 'a' .. 'h' outputs of a DMux8Way are 1-bit, so they may only be connected to 1-bit internal wires. (There is no way to tell the simulator that it should allocate an internal bus that will have wires connected to it later.)
More generally, though, this is not how you want to make your RAM8.
You don't need to demultiplex "in". In hardware, you can directly connect a circuit input to all the pats that may need it. If an individual part is not supposed to do anything with its input, it will ignore the value that is connected to it.
the addressed register gets the value of 'in'. Now, won't the value for the seven non-addressed registers be overwritten by 0000 in this case?
That is correct. Therefore, this is not a correct implementation.
What should the "load" pin for the non-addressed Registers be? You can't directly connect load=load. There is a part that will directly generate the load signals required for the Registers.
--Mark
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Thank you for your hint. I was able to implement a working code. I would like to know whether this code gives the best Performance/(Area*power), or whether there is a better implementation. My code is as follows.
Not(in=address[0], out=notAddr0);
Not(in=address[1], out=notAddr1);
Not(in=address[2], out=notAddr2);
And(a=notAddr0, b=load, out=midOutput1a0);
And(a=notAddr1, b=load, out=midOutput1b0);
And(a=notAddr2, b=load, out=midOutput1c0);
And(a=midOutput1a0, b=midOutput1b0, out=midOutput2a0);
And(a=midOutput1c0, b=midOutput2a0, out=loader0);
Register(in=in, load=loader0, out=regOut0);
And(a=address[0], b=load, out=midOutput1a1);
And(a=notAddr1, b=load, out=midOutput1b1);
And(a=notAddr2, b=load, out=midOutput1c1);
And(a=midOutput1a1, b=midOutput1b1, out=midOutput2a1);
And(a=midOutput1c1, b=midOutput2a1, out=loader1);
Register(in=in, load=loader1, out=regOut1);
And(a=notAddr0, b=load, out=midOutput1a2);
And(a=address[1], b=load, out=midOutput1b2);
And(a=notAddr2, b=load, out=midOutput1c2);
And(a=midOutput1a2, b=midOutput1b2, out=midOutput2a2);
And(a=midOutput1c2, b=midOutput2a2, out=loader2);
Register(in=in, load=loader2, out=regOut2);
And(a=address[0], b=load, out=midOutput1a3);
And(a=address[1], b=load, out=midOutput1b3);
And(a=notAddr2, b=load, out=midOutput1c3);
And(a=midOutput1a3, b=midOutput1b3, out=midOutput2a3);
And(a=midOutput1c3, b=midOutput2a3, out=loader3);
Register(in=in, load=loader3, out=regOut3);
And(a=notAddr0, b=load, out=midOutput1a4);
And(a=notAddr1, b=load, out=midOutput1b4);
And(a=address[2], b=load, out=midOutput1c4);
And(a=midOutput1a4, b=midOutput1b4, out=midOutput2a4);
And(a=midOutput1c4, b=midOutput2a4, out=loader4);
Register(in=in, load=loader4, out=regOut4);
And(a=address[0], b=load, out=midOutput1a5);
And(a=notAddr1, b=load, out=midOutput1b5);
And(a=address[2], b=load, out=midOutput1c5);
And(a=midOutput1a5, b=midOutput1b5, out=midOutput2a5);
And(a=midOutput1c5, b=midOutput2a5, out=loader5);
Register(in=in, load=loader5, out=regOut5);
And(a=notAddr0, b=load, out=midOutput1a6);
And(a=address[1], b=load, out=midOutput1b6);
And(a=address[2], b=load, out=midOutput1c6);
And(a=midOutput1a6, b=midOutput1b6, out=midOutput2a6);
And(a=midOutput1c6, b=midOutput2a6, out=loader6);
Register(in=in, load=loader6, out=regOut6);
And(a=address[0], b=load, out=midOutput1a7);
And(a=address[1], b=load, out=midOutput1b7);
And(a=address[2], b=load, out=midOutput1c7);
And(a=midOutput1a7, b=midOutput1b7, out=midOutput2a7);
And(a=midOutput1c7, b=midOutput2a7, out=loader7);
Register(in=in, load=loader7, out=regOut7);
Mux8Way16(a=regOut0, b=regOut1, c=regOut2, d=regOut3, e=regOut4, f=regOut5, g=regOut6, h=regOut7, sel=address, out=out);
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Administrator
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Way too much work. You built a part in project 1 that replaces all the Nots and Ands.
--Mark
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Locked
